📄 shiyan3gai.rpt
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Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
D25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 18/22( 81%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 39/96 ( 40%)
Total logic cells used: 84/1152 ( 7%)
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 3.27/4 ( 81%)
Total fan-in: 275/4608 ( 5%)
Total input pins required: 15
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 84
Total flipflops required: 26
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 17/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 8 8 7 0 0 0 0 0 0 25/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 8 6 8 8 0 7 6 0 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 59/8
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 6 8 8 0 7 6 0 8 0 8 8 2 0 0 8 8 7 0 0 0 0 0 0 84/8
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 13 INPUT 0 0 0 17 clk_cdu
95 - - B -- INPUT 0 0 0 8 clr_cdu
70 - - - 05 INPUT 0 0 0 1 cp161ldar
9 - - B -- BIDIR 0 1 0 2 d0
10 - - B -- BIDIR 0 1 0 2 d1
12 - - C -- BIDIR 0 1 0 2 d2
13 - - C -- BIDIR 0 1 0 2 d3
17 - - D -- BIDIR 0 1 0 2 d4
18 - - D -- BIDIR 0 1 0 2 d5
19 - - D -- BIDIR 0 1 0 2 d6
20 - - D -- BIDIR 0 1 0 2 d7
92 - - C -- INPUT 0 0 0 5 en_cdu
72 - - - 03 INPUT 0 0 0 1 LDAR
79 - - F -- INPUT 0 0 0 10 MEMENAB
82 - - E -- INPUT 0 0 0 9 pc_bus
78 - - F -- INPUT 0 0 0 10 RD
125 - - - -- INPUT G 0 0 0 0 scan_clk
91 - - C -- INPUT 0 0 0 2 scan_clr
83 - - E -- INPUT 0 0 0 9 sw_bus
73 - - - 01 INPUT 0 0 0 1 WE
86 - - E -- INPUT 0 0 0 8 161clr
87 - - E -- INPUT 0 0 0 8 161load
88 - - D -- INPUT 0 0 0 1 161pc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - D -- OUTPUT 0 1 0 0 adr0
22 - - D -- OUTPUT 0 1 0 0 adr1
23 - - D -- OUTPUT 0 1 0 0 adr2
26 - - E -- OUTPUT 0 1 0 0 adr3
27 - - E -- OUTPUT 0 1 0 0 adr4
28 - - E -- OUTPUT 0 1 0 0 adr5
29 - - E -- OUTPUT 0 1 0 0 adr6
30 - - F -- OUTPUT 0 1 0 0 adr7
9 - - B -- TRI 0 1 0 2 d0
10 - - B -- TRI 0 1 0 2 d1
12 - - C -- TRI 0 1 0 2 d2
13 - - C -- TRI 0 1 0 2 d3
17 - - D -- TRI 0 1 0 2 d4
18 - - D -- TRI 0 1 0 2 d5
19 - - D -- TRI 0 1 0 2 d6
20 - - D -- TRI 0 1 0 2 d7
8 - - A -- OUTPUT 0 1 0 0 q0
102 - - A -- OUTPUT 0 1 0 0 q1
51 - - - 14 OUTPUT 0 1 0 0 seg_a
49 - - - 14 OUTPUT 0 1 0 0 seg_b
48 - - - 15 OUTPUT 0 1 0 0 seg_c
47 - - - 16 OUTPUT 0 1 0 0 seg_d
46 - - - 17 OUTPUT 0 1 0 0 seg_e
44 - - - 18 OUTPUT 0 1 0 0 seg_f
43 - - - 18 OUTPUT 0 1 0 0 seg_g
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 6 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_0
- - 5 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_1
- - 2 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_2
- - 7 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_3
- - 3 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_4
- - 1 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_5
- - 8 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_6
- - 4 D -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_7
- 3 - D 08 AND2 3 0 0 8 |LPM_RAM_IO:57|:91
- 7 - D 02 DFFE + 1 0 1 5 |scan:40|:34
- 2 - D 02 DFFE + 1 1 1 4 |scan:40|:42
- 4 - D 02 OR2 0 4 0 17 |scan:40|:64
- 6 - D 02 OR2 0 4 0 17 |scan:40|:65
- 5 - D 02 OR2 0 4 0 16 |scan:40|:66
- 8 - D 02 OR2 ! 0 4 0 17 |scan:40|:67
- 6 - B 18 AND2 0 4 0 1 |scan:40|:92
- 7 - B 17 AND2 0 4 0 1 |scan:40|:104
- 7 - B 18 AND2 0 4 0 1 |scan:40|:116
- 3 - B 16 AND2 0 4 0 3 |scan:40|:128
- 8 - B 16 AND2 0 4 0 1 |scan:40|:152
- 5 - B 17 AND2 0 4 0 2 |scan:40|:176
- 5 - B 18 AND2 0 4 0 3 |scan:40|:224
- 4 - B 18 AND2 0 4 0 1 |scan:40|:236
- 8 - B 17 AND2 0 4 0 1 |scan:40|:248
- 2 - B 16 OR2 s 0 4 0 1 |scan:40|~283~1
- 2 - B 13 OR2 0 3 1 0 |scan:40|:283
- 7 - B 16 OR2 s 0 4 0 2 |scan:40|~286~1
- 1 - B 16 OR2 s 0 4 0 2 |scan:40|~286~2
- 4 - B 13 OR2 0 3 1 0 |scan:40|:286
- 3 - B 18 OR2 s 0 2 0 1 |scan:40|~289~1
- 6 - B 17 OR2 s 0 4 0 1 |scan:40|~289~2
- 4 - B 17 OR2 s 0 4 0 1 |scan:40|~289~3
- 5 - B 16 OR2 0 4 1 0 |scan:40|:289
- 4 - B 16 OR2 s 0 4 0 1 |scan:40|~292~1
- 6 - B 16 OR2 0 4 1 0 |scan:40|:292
- 2 - B 18 OR2 0 3 1 0 |scan:40|:295
- 3 - B 17 AND2 s 0 3 0 2 |scan:40|~298~1
- 1 - B 17 OR2 s 0 4 0 2 |scan:40|~298~2
- 1 - B 18 OR2 0 4 1 0 |scan:40|:298
- 2 - B 17 OR2 0 4 1 0 |scan:40|:301
- 3 - D 10 DFFE 2 3 0 4 |16counter:34|74161:4|f74161:sub|QA (|16counter:34|74161:4|f74161:sub|:9)
- 2 - D 10 DFFE 2 3 0 3 |16counter:34|74161:4|f74161:sub|QB (|16counter:34|74161:4|f74161:sub|:87)
- 5 - D 10 AND2 0 4 0 2 |16counter:34|74161:4|f74161:sub|:96
- 4 - D 10 DFFE 2 1 0 3 |16counter:34|74161:4|f74161:sub|QC (|16counter:34|74161:4|f74161:sub|:99)
- 6 - D 10 DFFE 2 2 0 2 |16counter:34|74161:4|f74161:sub|QD (|16counter:34|74161:4|f74161:sub|:110)
- 4 - D 04 DFFE 3 0 0 5 |16counter:35|74161:4|f74161:sub|QA (|16counter:35|74161:4|f74161:sub|:9)
- 5 - D 04 AND2 1 2 0 3 |16counter:35|74161:4|f74161:sub|:84
- 6 - D 04 DFFE 3 1 0 4 |16counter:35|74161:4|f74161:sub|QB (|16counter:35|74161:4|f74161:sub|:87)
- 1 - D 10 AND2 0 2 0 2 |16counter:35|74161:4|f74161:sub|:94
- 1 - D 04 DFFE 3 2 0 5 |16counter:35|74161:4|f74161:sub|QC (|16counter:35|74161:4|f74161:sub|:99)
- 8 - D 10 DFFE 3 2 0 5 |16counter:35|74161:4|f74161:sub|QD (|16counter:35|74161:4|f74161:sub|:110)
- 4 - D 07 AND2 2 0 0 8 :27
- 7 - D 10 AND2 2 0 0 8 :32
- 3 - D 12 DFFE 2 2 0 5 |74161:2|f74161:sub|QA (|74161:2|f74161:sub|:9)
- 7 - D 12 AND2 0 2 0 1 |74161:2|f74161:sub|:84
- 4 - D 12 DFFE 2 3 0 4 |74161:2|f74161:sub|QB (|74161:2|f74161:sub|:87)
- 1 - D 12 AND2 0 3 0 2 |74161:2|f74161:sub|:94
- 8 - D 12 DFFE 2 3 0 3 |74161:2|f74161:sub|QC (|74161:2|f74161:sub|:99)
- 5 - D 05 AND2 0 2 0 2 |74161:2|f74161:sub|:104
- 2 - D 12 DFFE 2 3 0 3 |74161:2|f74161:sub|QD (|74161:2|f74161:sub|:110)
- 1 - D 05 DFFE 2 3 0 3 |74161:3|f74161:sub|QA (|74161:3|f74161:sub|:9)
- 6 - D 05 AND2 0 2 0 2 |74161:3|f74161:sub|:80
- 7 - D 05 AND2 0 2 0 2 |74161:3|f74161:sub|:84
- 2 - D 05 DFFE 2 3 0 3 |74161:3|f74161:sub|QB (|74161:3|f74161:sub|:87)
- 8 - D 05 AND2 0 2 0 1 |74161:3|f74161:sub|:94
- 3 - D 05 DFFE 2 3 0 3 |74161:3|f74161:sub|QC (|74161:3|f74161:sub|:99)
- 4 - D 05 DFFE 2 3 0 2 |74161:3|f74161:sub|QD (|74161:3|f74161:sub|:110)
- 1 - D 03 OR2 4 0 0 0 |74244:4|~1~1~2
- 6 - D 08 OR2 s 2 2 0 1 |74244:4|~1~1~3~2
- 4 - D 08 OR2 2 2 1 0 |74244:4|~1~1~3
- 7 - D 04 OR2 s 2 2 0 1 |74244:4|~6~1~3~2
- 8 - D 04 OR2 2 2 1 0 |74244:4|~6~1~3
- 5 - D 12 OR2 s 2 2 0 1 |74244:4|~10~1~3~2
- 2 - D 08 OR2 2 2 1 0 |74244:4|~10~1~3
- 6 - D 03 OR2 s 2 2 0 1 |74244:4|~11~1~3~2
- 3 - D 03 OR2 2 2 1 0 |74244:4|~11~1~3
- 1 - D 02 OR2 s 2 2 0 1 |74244:4|~26~1~3~2
- 3 - D 02 OR2 2 2 1 0 |74244:4|~26~1~3
- 3 - D 04 OR2 s 2 2 0 1 |74244:4|~27~1~3~2
- 2 - D 04 OR2 2 2 1 0 |74244:4|~27~1~3
- 4 - D 03 OR2 s 2 2 0 1 |74244:4|~31~1~3~2
- 2 - D 03 OR2 2 2 1 0 |74244:4|~31~1~3
- 5 - D 08 OR2 s 2 2 0 1 |74244:4|~36~1~3~2
- 1 - D 08 OR2 2 2 1 0 |74244:4|~36~1~3
- 2 - D 07 DFFE 0 2 1 8 |74273:5|Q8 (|74273:5|:12)
- 8 - D 07 DFFE 0 2 1 8 |74273:5|Q7 (|74273:5|:13)
- 5 - D 03 DFFE 0 2 1 8 |74273:5|Q6 (|74273:5|:14)
- 3 - D 07 DFFE 0 2 1 8 |74273:5|Q5 (|74273:5|:15)
- 1 - D 07 DFFE 0 2 1 8 |74273:5|Q4 (|74273:5|:16)
- 6 - D 12 DFFE 0 2 1 8 |74273:5|Q3 (|74273:5|:17)
- 6 - D 07 DFFE 0 2 1 8 |74273:5|Q2 (|74273:5|:18)
- 5 - D 07 DFFE 0 2 1 8 |74273:5|Q1 (|74273:5|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 9/ 96( 9%) 0/ 48( 0%) 11/ 48( 22%) 1/16( 6%) 0/16( 0%) 2/16( 12%)
C: 6/ 96( 6%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 2/16( 12%)
D: 36/ 96( 37%) 29/ 48( 60%) 0/ 48( 0%) 1/16( 6%) 3/16( 18%) 4/16( 25%)
E: 8/ 96( 8%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
F: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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