📄 shiyan3gai.rpt
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Project Information d:\shiyan3\shiyan3gai.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 04/07/2008 18:19:01
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
shiyan3gai
EPF10K20TC144-3 15 17 8 2048 16 % 84 7 %
User Pins: 15 17 8
Project Information d:\shiyan3\shiyan3gai.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
Project Information d:\shiyan3\shiyan3gai.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
shiyan3gai@21 adr0
shiyan3gai@22 adr1
shiyan3gai@23 adr2
shiyan3gai@26 adr3
shiyan3gai@27 adr4
shiyan3gai@28 adr5
shiyan3gai@29 adr6
shiyan3gai@30 adr7
shiyan3gai@122 clk_cdu
shiyan3gai@95 clr_cdu
shiyan3gai@70 cp161ldar
shiyan3gai@9 d0
shiyan3gai@10 d1
shiyan3gai@12 d2
shiyan3gai@13 d3
shiyan3gai@17 d4
shiyan3gai@18 d5
shiyan3gai@19 d6
shiyan3gai@20 d7
shiyan3gai@92 en_cdu
shiyan3gai@72 LDAR
shiyan3gai@79 MEMENAB
shiyan3gai@82 pc_bus
shiyan3gai@8 q0
shiyan3gai@102 q1
shiyan3gai@78 RD
shiyan3gai@125 scan_clk
shiyan3gai@91 scan_clr
shiyan3gai@51 seg_a
shiyan3gai@49 seg_b
shiyan3gai@48 seg_c
shiyan3gai@47 seg_d
shiyan3gai@46 seg_e
shiyan3gai@44 seg_f
shiyan3gai@43 seg_g
shiyan3gai@83 sw_bus
shiyan3gai@73 WE
shiyan3gai@86 161clr
shiyan3gai@87 161load
shiyan3gai@88 161pc
Project Information d:\shiyan3\shiyan3gai.rpt
** EMBEDDED ARRAYS **
|LPM_RAM_IO:57|altram:sram|content: MEMORY (
width = 8;
depth = 256;
segmentsize = 256;
mode = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0;
)
OF SEGMENTS (
|LPM_RAM_IO:57|altram:sram|segment0_7,
|LPM_RAM_IO:57|altram:sram|segment0_6,
|LPM_RAM_IO:57|altram:sram|segment0_5,
|LPM_RAM_IO:57|altram:sram|segment0_4,
|LPM_RAM_IO:57|altram:sram|segment0_3,
|LPM_RAM_IO:57|altram:sram|segment0_2,
|LPM_RAM_IO:57|altram:sram|segment0_1,
|LPM_RAM_IO:57|altram:sram|segment0_0
);
Project Information d:\shiyan3\shiyan3gai.rpt
** FILE HIERARCHY **
|74244:4|
|74244:1|
|74161:3|
|74161:3|f74161:sub|
|74161:2|
|74161:2|f74161:sub|
|74273:5|
|16counter:35|
|16counter:35|74161:4|
|16counter:35|74161:4|f74161:sub|
|16counter:34|
|16counter:34|74161:4|
|16counter:34|74161:4|f74161:sub|
|scan:40|
|scan:40|lpm_add_sub:318|
|scan:40|lpm_add_sub:318|addcore:adder|
|scan:40|lpm_add_sub:318|altshift:result_ext_latency_ffs|
|scan:40|lpm_add_sub:318|altshift:carry_ext_latency_ffs|
|scan:40|lpm_add_sub:318|altshift:oflow_ext_latency_ffs|
|lpm_ram_io:57|
|lpm_ram_io:57|altram:sram|
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
***** Logic for device 'shiyan3gai' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R s R R R R R R R R R R R R
E E E E E E E E E E E E E E c c E E E E E E E E E E E E
S S S S S S S S S S S S S S G G a G V l S S S S S S S S S S S S
E E E E E G E E E E V E E E E G E N N n N C k E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N R D D _ D C _ R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D V I I c I I c V V V V V V C V V V V V V
E E E E E I E E E E I E E E E I E N N l N N d E E E E E E I E E E E E E
D D D D D O D D D D O D D D D O D T T k T T u D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | q1
q0 | 8 101 | RESERVED
d0 | 9 100 | RESERVED
d1 | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
d2 | 12 97 | RESERVED
d3 | 13 96 | RESERVED
RESERVED | 14 95 | clr_cdu
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
d4 | 17 92 | en_cdu
d5 | 18 91 | scan_clr
d6 | 19 EPF10K20TC144-3 90 | RESERVED
d7 | 20 89 | RESERVED
adr0 | 21 88 | 161pc
adr1 | 22 87 | 161load
adr2 | 23 86 | 161clr
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
adr3 | 26 83 | sw_bus
adr4 | 27 82 | pc_bus
adr5 | 28 81 | RESERVED
adr6 | 29 80 | RESERVED
adr7 | 30 79 | MEMENAB
RESERVED | 31 78 | RD
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | WE
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R s s V s s s s G s V V G G G G G R R V R R R R G R R R c V L
E E E N E E e e C e e e e N e C C N N N N N E E C E E E E N E E E p C D
S S S D S S g g C g g g g D g C C D D D D D S S C S S S S D S S S 1 C A
E E E I E E _ _ I _ _ _ _ I _ I I I I I I I E E I E E E E I E E E 6 I R
R R R O R R g f O e d c b O a N N N N N N N R R O R R R R O R R R 1 O
V V V V V T T T T T T T V V V V V V V V V l
E E E E E E E E E E E E E E d
D D D D D D D D D D D D D D a
r
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\shiyan3\shiyan3gai.rpt
shiyan3gai
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
B16 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B17 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
B18 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
D2 8/ 8(100%) 6/ 8( 75%) 1/ 8( 12%) 1/2 1/2 15/22( 68%)
D3 6/ 8( 75%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
D4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 12/22( 54%)
D5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
D7 7/ 8( 87%) 4/ 8( 50%) 7/ 8( 87%) 1/2 0/2 8/22( 36%)
D8 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
D12 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 11/22( 50%)
Embedded Column Row
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