finish.rpt

用verilog语言写的拔河游戏机

08:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
14:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
15:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      5/24( 20%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
19:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      2/24(  8%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
21:      2/24(  8%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
22:      3/24( 12%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
23:      2/24(  8%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
24:      2/24(  8%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                     e:\xyq\maxplus\sy4\finish.rpt
finish

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       12         clk
LCELL        8         :6
LCELL        8         :7
LCELL        8         :8
LCELL        8         :9


Device-Specific Information:                     e:\xyq\maxplus\sy4\finish.rpt
finish

** EQUATIONS **

ALU_BUS  : INPUT;
cir      : INPUT;
cir_181  : INPUT;
clk      : INPUT;
CN       : INPUT;
cp_t     : INPUT;
en       : INPUT;
en_181   : INPUT;
LDDR1    : INPUT;
LDDR2    : INPUT;
LDR4     : INPUT;
LDR5     : INPUT;
M        : INPUT;
R4_BUS   : INPUT;
R5_BUS   : INPUT;
scan_clk : INPUT;
SW_BUS   : INPUT;

-- Node name is 'CN4' 
-- Equation name is 'CN4', type is output 
CN4      =  _LC5_F19;

-- Node name is 'D0' 
-- Equation name is 'D0', type is bidir 
D0       = TRI(_LC3_F17,  _LC1_F22);

-- Node name is 'D1' 
-- Equation name is 'D1', type is bidir 
D1       = TRI(_LC8_F8,  _LC1_F22);

-- Node name is 'D2' 
-- Equation name is 'D2', type is bidir 
D2       = TRI(_LC6_F15,  _LC1_F22);

-- Node name is 'D3' 
-- Equation name is 'D3', type is bidir 
D3       = TRI(_LC8_F23,  _LC1_F22);

-- Node name is 'D4' 
-- Equation name is 'D4', type is bidir 
D4       = TRI(_LC1_F24,  _LC1_F22);

-- Node name is 'D5' 
-- Equation name is 'D5', type is bidir 
D5       = TRI(_LC8_F22,  _LC1_F22);

-- Node name is 'D6' 
-- Equation name is 'D6', type is bidir 
D6       = TRI(_LC1_F21,  _LC1_F22);

-- Node name is 'D7' 
-- Equation name is 'D7', type is bidir 
D7       = TRI(_LC8_F19,  _LC1_F22);

-- Node name is 'GW' 
-- Equation name is 'GW', type is output 
GW       = !_LC7_F8;

-- Node name is 'GW~1' 
-- Equation name is 'GW~1', location is LC7_F8, type is buried.
-- synthesized logic cell 
_LC7_F8  = LCELL( scan_clk);

-- Node name is 'seg_a' 
-- Equation name is 'seg_a', type is output 
seg_a    =  _LC7_B13;

-- Node name is 'seg_b' 
-- Equation name is 'seg_b', type is output 
seg_b    =  _LC4_B13;

-- Node name is 'seg_c' 
-- Equation name is 'seg_c', type is output 
seg_c    =  _LC2_B15;

-- Node name is 'seg_d' 
-- Equation name is 'seg_d', type is output 
seg_d    =  _LC2_B16;

-- Node name is 'seg_e' 
-- Equation name is 'seg_e', type is output 
seg_e    =  _LC5_B18;

-- Node name is 'seg-f' 
-- Equation name is 'seg-f', type is output 
seg-f    =  _LC3_B18;

-- Node name is 'seg_g' 
-- Equation name is 'seg_g', type is output 
seg_g    =  _LC8_B18;

-- Node name is 'SW' 
-- Equation name is 'SW', type is output 
SW       =  _LC3_F8;

-- Node name is 'SW~1' 
-- Equation name is 'SW~1', location is LC3_F8, type is buried.
-- synthesized logic cell 
_LC3_F8  = LCELL( scan_clk);

-- Node name is 's0' 
-- Equation name is 's0', type is output 
s0       =  _LC4_F18;

-- Node name is 's1' 
-- Equation name is 's1', type is output 
s1       =  _LC8_F18;

-- Node name is 's2' 
-- Equation name is 's2', type is output 
s2       =  _LC1_F18;

-- Node name is 's3' 
-- Equation name is 's3', type is output 
s3       =  _LC2_F18;

-- Node name is '|BCD_7SEG:81|:372' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = LCELL( _EQ001);
  _EQ001 =  _LC1_F3 &  _LC1_F8 &  _LC4_F11 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:444' 
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ002);
  _EQ002 =  _LC1_F3 & !_LC1_F8 & !_LC4_F11 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:456' 
-- Equation name is '_LC1_B18', type is buried 
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ003);
  _EQ003 = !_LC4_F11
         #  _LC1_F3
         # !_LC1_F8
         # !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:492' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ004);
  _EQ004 = !_LC1_F3 & !_LC1_F8 &  _LC4_F11 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:528' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ005);
  _EQ005 = !_LC1_F3 & !_LC1_F8 & !_LC4_F11 &  _LC8_F11;

-- Node name is '|BCD_7SEG:81|:540' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = LCELL( _EQ006);
  _EQ006 = !_LC1_F3 & !_LC1_F8 & !_LC4_F11 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:545' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ007);
  _EQ007 = !_LC1_B18 & !_LC2_B18 & !_LC4_B18;

-- Node name is '|BCD_7SEG:81|~567~1' 
-- Equation name is '_LC6_B16', type is buried 
-- synthesized logic cell 
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ008);
  _EQ008 =  _LC4_F11
         # !_LC1_F3
         # !_LC1_F8 & !_LC8_F11
         #  _LC1_F8 &  _LC8_F11;

-- Node name is '|BCD_7SEG:81|:591' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = LCELL( _EQ009);
  _EQ009 =  _LC1_F3 &  _LC1_F8
         #  _LC1_F8 &  _LC4_F11 & !_LC8_F11
         # !_LC1_F3 & !_LC1_F8 &  _LC4_F11
         # !_LC1_F3 &  _LC4_F11 & !_LC8_F11
         #  _LC1_F3 & !_LC4_F11
         # !_LC1_F8 & !_LC4_F11 & !_LC8_F11
         # !_LC1_F3 & !_LC1_F8 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|:633' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = LCELL( _EQ010);
  _EQ010 =  _LC1_F3 &  _LC1_F8
         #  _LC1_F3 &  _LC4_F11
         #  _LC1_F8 & !_LC8_F11
         # !_LC4_F11 & !_LC8_F11
         #  _LC1_F3 & !_LC8_F11
         # !_LC1_F3 & !_LC1_F8 & !_LC4_F11;

-- Node name is '|BCD_7SEG:81|:639' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ011);
  _EQ011 = !_LC4_B18 &  _LC6_B18
         #  _LC2_B18;

-- Node name is '|BCD_7SEG:81|:663' 
-- Equation name is '_LC7_B16', type is buried 
_LC7_B16 = LCELL( _EQ012);
  _EQ012 =  _LC5_B16
         #  _LC1_B13 & !_LC6_B16
         # !_LC2_B13 & !_LC6_B16;

-- Node name is '|BCD_7SEG:81|:680' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ013);
  _EQ013 = !_LC1_B18 & !_LC4_B16 &  _LC7_B16
         #  _LC3_B13 & !_LC4_B16;

-- Node name is '|BCD_7SEG:81|:687' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = LCELL( _EQ014);
  _EQ014 = !_LC4_B18 &  _LC8_B16
         #  _LC3_B16 & !_LC4_B18
         #  _LC2_B18;

-- Node name is '|BCD_7SEG:81|~726~1' 
-- Equation name is '_LC3_B13', type is buried 
-- synthesized logic cell 
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ015);
  _EQ015 = !_LC4_F11
         #  _LC1_F3
         # !_LC1_F8 & !_LC8_F11
         #  _LC1_F8 &  _LC8_F11;

-- Node name is '|BCD_7SEG:81|:734' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = LCELL( _EQ016);
  _EQ016 = !_LC1_F8 &  _LC4_F11 &  _LC8_F11
         #  _LC1_F8 & !_LC4_F11 &  _LC8_F11
         # !_LC1_F3 & !_LC1_F8 &  _LC4_F11
         # !_LC1_F3 &  _LC4_F11 & !_LC8_F11
         # !_LC1_F3 &  _LC1_F8 &  _LC8_F11
         #  _LC1_F3 & !_LC1_F8 &  _LC8_F11
         #  _LC1_F3 & !_LC4_F11;

-- Node name is '|BCD_7SEG:81|:735' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ017);
  _EQ017 =  _LC4_B18
         #  _LC2_B18
         #  _LC5_B13;

-- Node name is '|BCD_7SEG:81|:755' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = LCELL( _EQ018);
  _EQ018 =  _LC1_F3 & !_LC1_F8 &  _LC4_F11 &  _LC8_F11
         #  _LC1_F3 &  _LC1_F8 &  _LC4_F11 & !_LC8_F11;

-- Node name is '|BCD_7SEG:81|~783~1' 
-- Equation name is '_LC1_B16', type is buried 
-- synthesized logic cell 
_LC1_B16 = LCELL( _EQ019);