📄 finish.rpt
字号:
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 1 8 0 7 0 0 0 0 0 0 24/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 2 8 1 1 0 0 8 0 0 8 0 0 1 8 8 8 8 8 8 8 8 8 8 7 116/0
Total: 0 2 8 1 1 0 0 8 0 0 8 0 0 9 8 9 16 8 15 8 8 8 8 8 7 140/0
Device-Specific Information: e:\xyq\maxplus\sy4\finish.rpt
finish
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
82 - - E -- INPUT 0 0 0 9 ALU_BUS
95 - - B -- INPUT 0 0 0 8 cir
79 - - F -- INPUT 0 0 0 4 cir_181
122 - - - 13 INPUT 0 0 0 12 clk
73 - - - 01 INPUT 0 0 0 2 CN
128 - - - 13 INPUT 0 0 0 4 cp_t
31 - - F -- BIDIR 0 1 0 4 D0
32 - - F -- BIDIR 0 1 0 4 D1
33 - - F -- BIDIR 0 1 0 4 D2
36 - - - 24 BIDIR 0 1 0 4 D3
37 - - - 23 BIDIR 0 1 0 4 D4
38 - - - 22 BIDIR 0 1 0 4 D5
39 - - - 21 BIDIR 0 1 0 4 D6
41 - - - 20 BIDIR 0 1 0 4 D7
92 - - C -- INPUT 0 0 0 4 en
78 - - F -- INPUT 0 0 0 3 en_181
88 - - D -- INPUT 0 0 0 1 LDDR1
89 - - C -- INPUT 0 0 0 1 LDDR2
86 - - E -- INPUT 0 0 0 1 LDR4
87 - - E -- INPUT 0 0 0 1 LDR5
72 - - - 03 INPUT 0 0 0 8 M
80 - - F -- INPUT 0 0 0 9 R4_BUS
81 - - F -- INPUT 0 0 0 9 R5_BUS
125 - - - -- INPUT 0 0 0 6 scan_clk
83 - - E -- INPUT 0 0 0 9 SW_BUS
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\finish.rpt
finish
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - D -- OUTPUT 0 1 0 0 CN4
31 - - F -- TRI 0 1 0 4 D0
32 - - F -- TRI 0 1 0 4 D1
33 - - F -- TRI 0 1 0 4 D2
36 - - - 24 TRI 0 1 0 4 D3
37 - - - 23 TRI 0 1 0 4 D4
38 - - - 22 TRI 0 1 0 4 D5
39 - - - 21 TRI 0 1 0 4 D6
41 - - - 20 TRI 0 1 0 4 D7
8 - - A -- OUTPUT 0 1 0 0 GW
51 - - - 14 OUTPUT 0 1 0 0 seg_a
49 - - - 14 OUTPUT 0 1 0 0 seg_b
48 - - - 15 OUTPUT 0 1 0 0 seg_c
47 - - - 16 OUTPUT 0 1 0 0 seg_d
46 - - - 17 OUTPUT 0 1 0 0 seg_e
44 - - - 18 OUTPUT 0 1 0 0 seg-f
43 - - - 18 OUTPUT 0 1 0 0 seg_g
102 - - A -- OUTPUT 0 1 0 0 SW
9 - - B -- OUTPUT 0 1 0 0 s0
10 - - B -- OUTPUT 0 1 0 0 s1
12 - - C -- OUTPUT 0 1 0 0 s2
13 - - C -- OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\finish.rpt
finish
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 13 AND2 0 4 0 1 |BCD_7SEG:81|:372
- 5 - B 16 AND2 0 4 0 1 |BCD_7SEG:81|:444
- 1 - B 18 OR2 ! 0 4 0 2 |BCD_7SEG:81|:456
- 4 - B 16 AND2 0 4 0 2 |BCD_7SEG:81|:492
- 4 - B 18 AND2 0 4 0 5 |BCD_7SEG:81|:528
- 2 - B 18 AND2 0 4 0 5 |BCD_7SEG:81|:540
- 8 - B 18 AND2 0 3 1 0 |BCD_7SEG:81|:545
- 6 - B 16 OR2 s ! 0 4 0 1 |BCD_7SEG:81|~567~1
- 3 - B 18 OR2 0 4 1 0 |BCD_7SEG:81|:591
- 6 - B 18 OR2 0 4 0 1 |BCD_7SEG:81|:633
- 5 - B 18 OR2 0 3 1 0 |BCD_7SEG:81|:639
- 7 - B 16 OR2 0 4 0 1 |BCD_7SEG:81|:663
- 8 - B 16 OR2 0 4 0 1 |BCD_7SEG:81|:680
- 2 - B 16 OR2 0 4 1 0 |BCD_7SEG:81|:687
- 3 - B 13 OR2 s ! 0 4 0 2 |BCD_7SEG:81|~726~1
- 5 - B 13 OR2 0 4 0 1 |BCD_7SEG:81|:734
- 2 - B 15 OR2 0 3 1 0 |BCD_7SEG:81|:735
- 8 - B 13 OR2 0 4 0 1 |BCD_7SEG:81|:755
- 1 - B 16 OR2 s 0 4 0 1 |BCD_7SEG:81|~783~1
- 4 - B 13 OR2 0 4 1 0 |BCD_7SEG:81|:783
- 2 - B 13 OR2 ! 0 4 0 1 |BCD_7SEG:81|:803
- 6 - B 13 OR2 s 0 4 0 1 |BCD_7SEG:81|~816~1
- 3 - B 16 AND2 s 0 3 0 2 |BCD_7SEG:81|~825~1
- 7 - B 13 OR2 0 4 1 0 |BCD_7SEG:81|:831
- 4 - F 18 DFFE 3 0 1 10 |cdu16:50|74163:8|f74163:sub|QA (|cdu16:50|74163:8|f74163:sub|:34)
- 8 - F 18 DFFE 3 1 1 9 |cdu16:50|74163:8|f74163:sub|QB (|cdu16:50|74163:8|f74163:sub|:111)
- 7 - F 18 AND2 1 2 0 2 |cdu16:50|74163:8|f74163:sub|:119
- 1 - F 18 DFFE 2 1 1 9 |cdu16:50|74163:8|f74163:sub|QC (|cdu16:50|74163:8|f74163:sub|:122)
- 2 - F 18 DFFE 2 2 1 8 |cdu16:50|74163:8|f74163:sub|QD (|cdu16:50|74163:8|f74163:sub|:134)
- 6 - F 11 DFFE 3 0 0 5 |cdu16:54|74163:8|f74163:sub|QA (|cdu16:54|74163:8|f74163:sub|:34)
- 5 - F 11 AND2 0 2 0 1 |cdu16:54|74163:8|f74163:sub|:106
- 1 - F 11 DFFE 3 1 0 4 |cdu16:54|74163:8|f74163:sub|QB (|cdu16:54|74163:8|f74163:sub|:111)
- 2 - F 11 AND2 0 3 0 4 |cdu16:54|74163:8|f74163:sub|:117
- 7 - F 11 DFFE 3 1 0 3 |cdu16:54|74163:8|f74163:sub|QC (|cdu16:54|74163:8|f74163:sub|:122)
- 7 - F 03 AND2 0 2 0 1 |cdu16:54|74163:8|f74163:sub|:128
- 4 - F 03 DFFE 3 1 0 5 |cdu16:54|74163:8|f74163:sub|QD (|cdu16:54|74163:8|f74163:sub|:134)
- 2 - F 03 DFFE 2 2 0 4 |cdu16:56|74163:8|f74163:sub|QA (|cdu16:56|74163:8|f74163:sub|:34)
- 3 - F 03 DFFE 2 2 0 3 |cdu16:56|74163:8|f74163:sub|QB (|cdu16:56|74163:8|f74163:sub|:111)
- 6 - F 03 AND2 0 4 0 2 |cdu16:56|74163:8|f74163:sub|:119
- 5 - F 03 DFFE 2 1 0 3 |cdu16:56|74163:8|f74163:sub|QC (|cdu16:56|74163:8|f74163:sub|:122)
- 8 - F 03 DFFE 2 2 0 2 |cdu16:56|74163:8|f74163:sub|QD (|cdu16:56|74163:8|f74163:sub|:134)
- 7 - F 08 LCELL s 1 0 1 0 GW~1
- 8 - F 11 OR2 ! 1 2 0 15 |saomiao:78|74157:1|Y1 (|saomiao:78|74157:1|:22)
- 1 - F 08 OR2 1 2 0 16 |saomiao:78|74157:1|Y2 (|saomiao:78|74157:1|:23)
- 4 - F 11 OR2 ! 1 2 0 16 |saomiao:78|74157:1|Y3 (|saomiao:78|74157:1|:24)
- 1 - F 03 OR2 1 2 0 16 |saomiao:78|74157:1|Y4 (|saomiao:78|74157:1|:25)
- 3 - F 08 LCELL s 1 0 1 0 SW~1
- 4 - F 14 AND2 2 0 0 8 :6
- 1 - F 14 AND2 2 0 0 8 :7
- 3 - F 14 AND2 2 0 0 8 :8
- 2 - F 14 AND2 2 0 0 8 :9
- 3 - F 20 OR2 0 4 0 2 |74181:46|:43
- 2 - F 16 OR2 0 4 0 3 |74181:46|:44
- 4 - F 20 OR2 0 4 0 3 |74181:46|:45
- 2 - F 20 OR2 0 4 0 2 |74181:46|:46
- 7 - F 16 OR2 0 4 0 3 |74181:46|:47
- 1 - F 20 OR2 0 4 0 2 |74181:46|:48
- 2 - F 19 OR2 0 4 0 2 |74181:46|:51
- 3 - F 19 OR2 0 4 0 2 |74181:46|:52
- 2 - F 21 OR2 s 0 4 0 2 |74181:46|~74~1
- 4 - F 19 OR2 1 2 0 1 |74181:46|:74
- 5 - F 21 OR2 s 0 3 0 1 |74181:46|~75~1
- 5 - F 19 OR2 0 4 1 0 |74181:46|CN4 (|74181:46|:78)
- 2 - F 24 OR2 s 0 3 0 3 |74181:46|~79~1
- 5 - F 24 OR2 1 3 0 1 |74181:46|:80
- 4 - F 22 OR2 1 3 0 1 |74181:46|:81
- 6 - F 21 OR2 1 3 0 1 |74181:46|:82
- 2 - F 17 OR2 ! 0 4 0 2 |74181:47|:43
- 6 - F 18 OR2 ! 0 4 0 2 |74181:47|:44
- 2 - F 15 OR2 ! 0 4 0 3 |74181:47|:45
- 6 - F 22 OR2 ! 0 4 0 2 |74181:47|:46
- 5 - F 18 OR2 ! 0 4 0 2 |74181:47|:47
- 3 - F 15 OR2 ! 0 4 0 2 |74181:47|:48
- 3 - F 23 OR2 0 4 0 2 |74181:47|:51
- 6 - F 16 OR2 0 4 0 2 |74181:47|:52
- 2 - F 23 OR2 1 2 0 1 |74181:47|:74
- 1 - F 17 OR2 s 1 2 0 2 |74181:47|CN4~1 (|74181:47|~78~1)
- 4 - F 15 OR2 s 0 3 0 2 |74181:47|CN4~2 (|74181:47|~78~2)
- 1 - F 15 OR2 s 0 2 0 2 |74181:47|CN4~3 (|74181:47|~78~3)
- 4 - F 23 OR2 ! 0 4 0 2 |74181:47|CN4 (|74181:47|:78)
- 5 - F 17 OR2 s 2 1 0 1 |74181:47|~80~1
- 3 - F 18 OR2 1 3 0 1 |74181:47|:81
- 5 - F 15 OR2 1 3 0 1 |74181:47|:82
- 4 - F 17 OR2 s 2 2 0 1 |74244:48|~1~1~3~2
- 3 - F 17 OR2 1 3 1 0 |74244:48|~1~1~3
- 6 - F 17 OR2 1 2 0 1 |74244:48|~1~2
- 2 - F 08 OR2 s 2 2 0 1 |74244:48|~6~1~3~2
- 4 - F 08 OR2 s 1 2 0 1 |74244:48|~6~1~3~3
- 8 - F 08 OR2 1 2 1 0 |74244:48|~6~1~3
- 3 - F 11 OR2 s 2 2 0 1 |74244:48|~10~1~3~2
- 4 - F 02 OR2 s 1 2 0 1 |74244:48|~10~1~3~3
- 6 - F 15 OR2 1 2 1 0 |74244:48|~10~1~3
- 1 - F 23 OR2 s 2 2 0 1 |74244:48|~11~1~3~2
- 8 - F 23 OR2 1 3 1 0 |74244:48|~11~1~3
- 5 - F 23 OR2 1 3 0 1 |74244:48|~11~2
- 1 - F 19 OR2 s 2 2 0 1 |74244:48|~26~1~3~2
- 8 - F 19 OR2 1 3 1 0 |74244:48|~26~1~3
- 6 - F 19 OR2 1 3 0 1 |74244:48|~26~2
- 3 - F 21 OR2 s 2 2 0 1 |74244:48|~27~1~3~2
- 1 - F 21 OR2 1 3 1 0 |74244:48|~27~1~3
- 1 - F 22 OR2 4 0 0 0 |74244:48|~31~1~2
- 2 - F 22 OR2 s 2 2 0 1 |74244:48|~31~1~3~2
- 3 - F 22 OR2 s 1 2 0 1 |74244:48|~31~1~3~3
- 8 - F 22 OR2 1 2 1 0 |74244:48|~31~1~3
- 3 - F 24 OR2 s 2 2 0 1 |74244:48|~36~1~3~2
- 4 - F 24 OR2 s 1 2 0 1 |74244:48|~36~1~3~3
- 1 - F 24 OR2 1 2 1 0 |74244:48|~36~1~3
- 5 - F 14 DFFE 0 2 0 2 |74273:44|Q8 (|74273:44|:12)
- 8 - F 20 DFFE 0 2 0 2 |74273:44|Q7 (|74273:44|:13)
- 8 - F 16 DFFE 0 2 0 2 |74273:44|Q6 (|74273:44|:14)
- 6 - F 20 DFFE 0 2 0 2 |74273:44|Q5 (|74273:44|:15)
- 8 - F 13 DFFE 0 2 0 2 |74273:44|Q4 (|74273:44|:16)
- 8 - F 15 DFFE 0 2 0 2 |74273:44|Q3 (|74273:44|:17)
- 7 - F 14 DFFE 0 2 0 2 |74273:44|Q2 (|74273:44|:18)
- 1 - F 16 DFFE 0 2 0 2 |74273:44|Q1 (|74273:44|:19)
- 6 - F 14 DFFE 0 2 0 2 |74273:45|Q8 (|74273:45|:12)
- 7 - F 20 DFFE 0 2 0 2 |74273:45|Q7 (|74273:45|:13)
- 5 - F 16 DFFE 0 2 0 2 |74273:45|Q6 (|74273:45|:14)
- 5 - F 20 DFFE 0 2 0 2 |74273:45|Q5 (|74273:45|:15)
- 3 - F 16 DFFE 0 2 0 2 |74273:45|Q4 (|74273:45|:16)
- 7 - F 15 DFFE 0 2 0 2 |74273:45|Q3 (|74273:45|:17)
- 8 - F 14 DFFE 0 2 0 2 |74273:45|Q2 (|74273:45|:18)
- 4 - F 16 DFFE 0 2 0 2 |74273:45|Q1 (|74273:45|:19)
- 7 - F 17 DFFE 0 2 0 1 |74374:42|:13
- 5 - F 08 DFFE 0 2 0 1 |74374:42|:14
- 3 - F 04 DFFE 0 2 0 1 |74374:42|:15
- 6 - F 23 DFFE 0 2 0 1 |74374:42|:16
- 6 - F 24 DFFE 0 2 0 1 |74374:42|:17
- 5 - F 22 DFFE 0 2 0 1 |74374:42|:18
- 7 - F 21 DFFE 0 2 0 1 |74374:42|:19
- 1 - F 05 DFFE 0 2 0 1 |74374:42|:20
- 8 - F 17 DFFE 0 2 0 1 |74374:43|:13
- 6 - F 08 DFFE 0 2 0 1 |74374:43|:14
- 1 - F 02 DFFE 0 2 0 1 |74374:43|:15
- 7 - F 23 DFFE 0 2 0 1 |74374:43|:16
- 7 - F 24 DFFE 0 2 0 1 |74374:43|:17
- 7 - F 22 DFFE 0 2 0 1 |74374:43|:18
- 8 - F 21 DFFE 0 2 0 1 |74374:43|:19
- 7 - F 19 DFFE 0 2 0 1 |74374:43|:20
- 4 - F 21 OR2 1 1 0 1 |74374:43|~46~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\xyq\maxplus\sy4\finish.rpt
finish
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 9/ 48( 18%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
E: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
F: 40/ 96( 41%) 4/ 48( 8%) 33/ 48( 68%) 4/16( 25%) 0/16( 0%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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