📄 shiyan3gai2.rpt
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-- Node name is '|74244:4|~6~1~3~2'
-- Equation name is '_LC1_C16', type is buried
-- synthesized logic cell
_LC1_C16 = LCELL( _EQ060);
_EQ060 = _LC3_C20 & sw_bus
# pc_bus & sw_bus
# _LC3_C20 & _LC6_C16
# _LC6_C16 & pc_bus;
-- Node name is '|74244:4|~6~1~3'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = LCELL( _EQ061);
_EQ061 = _EC7_C & _LC1_C16
# _LC1_C16 & !MEMENAB
# _LC1_C16 & !RD;
-- Node name is '|74244:4|~10~1~3~2'
-- Equation name is '_LC4_C20', type is buried
-- synthesized logic cell
_LC4_C20 = LCELL( _EQ062);
_EQ062 = _LC6_C20 & sw_bus
# pc_bus & sw_bus
# _LC5_C16 & _LC6_C20
# _LC5_C16 & pc_bus;
-- Node name is '|74244:4|~10~1~3'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ063);
_EQ063 = _EC2_C & _LC4_C20
# _LC4_C20 & !MEMENAB
# _LC4_C20 & !RD;
-- Node name is '|74244:4|~11~1~3~2'
-- Equation name is '_LC8_C15', type is buried
-- synthesized logic cell
_LC8_C15 = LCELL( _EQ064);
_EQ064 = _LC1_C20 & sw_bus
# pc_bus & sw_bus
# _LC1_C20 & _LC3_C23
# _LC3_C23 & pc_bus;
-- Node name is '|74244:4|~11~1~3'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = LCELL( _EQ065);
_EQ065 = _EC4_C & _LC8_C15
# _LC8_C15 & !MEMENAB
# _LC8_C15 & !RD;
-- Node name is '|74244:4|~26~1~3~2'
-- Equation name is '_LC5_C15', type is buried
-- synthesized logic cell
_LC5_C15 = LCELL( _EQ066);
_EQ066 = _LC6_C24 & sw_bus
# pc_bus & sw_bus
# _LC6_C24 & _LC7_C23
# _LC7_C23 & pc_bus;
-- Node name is '|74244:4|~26~1~3'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ067);
_EQ067 = _EC5_C & _LC5_C15
# _LC5_C15 & !MEMENAB
# _LC5_C15 & !RD;
-- Node name is '|74244:4|~27~1~3~2'
-- Equation name is '_LC7_C15', type is buried
-- synthesized logic cell
_LC7_C15 = LCELL( _EQ068);
_EQ068 = _LC3_C24 & sw_bus
# pc_bus & sw_bus
# _LC2_C23 & _LC3_C24
# _LC2_C23 & pc_bus;
-- Node name is '|74244:4|~27~1~3'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = LCELL( _EQ069);
_EQ069 = _EC6_C & _LC7_C15
# _LC7_C15 & !MEMENAB
# _LC7_C15 & !RD;
-- Node name is '|74244:4|~31~1~3~2'
-- Equation name is '_LC4_C22', type is buried
-- synthesized logic cell
_LC4_C22 = LCELL( _EQ070);
_EQ070 = _LC2_C24 & sw_bus
# pc_bus & sw_bus
# _LC1_C23 & _LC2_C24
# _LC1_C23 & pc_bus;
-- Node name is '|74244:4|~31~1~3'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ071);
_EQ071 = _EC3_C & _LC4_C22
# _LC4_C22 & !MEMENAB
# _LC4_C22 & !RD;
-- Node name is '|74244:4|~36~1~3~2'
-- Equation name is '_LC3_C22', type is buried
-- synthesized logic cell
_LC3_C22 = LCELL( _EQ072);
_EQ072 = _LC1_C24 & sw_bus
# pc_bus & sw_bus
# _LC1_C24 & _LC6_C23
# _LC6_C23 & pc_bus;
-- Node name is '|74244:4|~36~1~3'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ073);
_EQ073 = _EC1_C & _LC3_C22
# _LC3_C22 & !MEMENAB
# _LC3_C22 & !RD;
-- Node name is '|74273:5|:19' = '|74273:5|Q1'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _LC2_C20, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:18' = '|74273:5|Q2'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = DFFE( _LC3_C20, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:17' = '|74273:5|Q3'
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = DFFE( _LC6_C20, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:16' = '|74273:5|Q4'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = DFFE( _LC1_C20, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:15' = '|74273:5|Q5'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _LC1_C24, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:14' = '|74273:5|Q6'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = DFFE( _LC2_C24, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:13' = '|74273:5|Q7'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE( _LC3_C24, _LC4_C13, VCC, VCC, VCC);
-- Node name is '|74273:5|:12' = '|74273:5|Q8'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = DFFE( _LC6_C24, _LC4_C13, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ074);
_EQ074 = !clk_cdu & LDAR;
-- Node name is ':32'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ075);
_EQ075 = clk_cdu & 161pc;
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_C', type is memory
_EC8_C = MEMORY_SEGMENT( d0, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_C', type is memory
_EC7_C = MEMORY_SEGMENT( d1, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_C', type is memory
_EC2_C = MEMORY_SEGMENT( d2, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_C', type is memory
_EC4_C = MEMORY_SEGMENT( d3, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_C', type is memory
_EC1_C = MEMORY_SEGMENT( d4, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_C', type is memory
_EC3_C = MEMORY_SEGMENT( d5, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_C', type is memory
_EC6_C = MEMORY_SEGMENT( d6, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_C', type is memory
_EC5_C = MEMORY_SEGMENT( d7, clk_cdu, VCC, _LC6_C15, VCC, _LC5_C13, _LC6_C13, _LC7_C20, _LC1_C13, _LC3_C13, _LC5_C22, _LC8_C13, _LC2_C13, VCC, VCC, VCC,);
Project Information d:\shiyan3\shiyan3gai2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,507K
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