fq_div.vhd

pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FQ_DIV IS
PORT(RESET: IN STD_LOGIC;
CLK1000: IN STD_LOGIC;
CLK_1000:OUT STD_LOGIC);
END FQ_DIV;
ARCHITECTURE ART OF FQ_DIV IS
BEGIN
PROCESS(CLK1000) IS
VARIABLE CNT1: INTEGER RANGE 0 TO 128;
BEGIN
IF CLK1000='1'AND CLK1000'EVENT THEN
IF RESET='1'THEN
IF CNT1<64 THEN
CLK_1000<='1';
CNT1:=CNT1+1;
ELSIF CNT1<127 THEN
CLK_1000<='0';
CNT1:=CNT1+1;
ELSE CNT1:=0;
END IF;
ELSE CNT1:=0;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;