⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 timer.vhd

📁 数字钟 六位数码管显示
💻 VHD
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY TIMER IS
  PORT( CLK5:IN STD_LOGIC;
        CLK3:IN STD_LOGIC;
         RST1:IN STD_LOGIC;
     SEG_SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
     SEG_DA :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
END TIMER;

ARCHITECTURE ADO OF TIMER IS
COMPONENT CNT10
   PORT(CLK:IN STD_LOGIC;
        RST:IN STD_LOGIC;
        CIN:IN STD_LOGIC;
      CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT :OUT STD_LOGIC
        );
  END COMPONENT;
COMPONENT CNT6
   PORT(CLK :IN STD_LOGIC;
        RST :IN STD_LOGIC;
        CIN :IN STD_LOGIC;
     CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT:OUT STD_LOGIC
         );
  END COMPONENT;
COMPONENT CNT2
   PORT(CLK: IN STD_LOGIC;
        RST: IN STD_LOGIC;
        CIN: IN STD_LOGIC;
    CNT_VAL:INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COUT :OUT STD_LOGIC
        );
  END COMPONENT;
COMPONENT CNT4
  PORT (CLK:IN STD_LOGIC;
        RST:IN STD_LOGIC;
        CIN:IN STD_LOGIC;
    CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       COUT:OUT STD_LOGIC
        );
 END COMPONENT;
SIGNAL SEG_BUF1,SEG_BUF2,SEG_BUF3,SEG_BUF4:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEG_BUF5,SEG_BUF6,SEG_BUF7,SEG_BUF8:STD_LOGIC_VECTOR(3 DOWNTO 0); 
SIGNAL SEG_CNT :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL SEG_TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT:STD_LOGIC_VECTOR(5 DOWNTO 0);  
SIGNAL CLK:STD_LOGIC;
  BEGIN
 
  PROCESS (CLK3)
       BEGIN
          IF CLK3'EVENT AND CLK3='1' THEN
                   CLK<=NOT CLK ;
          END IF;
       END PROCESS;  
  PROCESS (CLK, RST1)
       BEGIN
                 IF CLK'EVENT AND CLK='1' THEN   
                         IF  RST1='1'  THEN
                              SEG_CNT<="000";
                         ELSE 
                              SEG_CNT<=SEG_CNT+1;
                         END IF;
                 END IF;
       END PROCESS;
      SEG_SEL<=SEG_CNT;
      SEG_BUF3<="1111";
      SEG_BUF6<="1111";
     PROCESS(SEG_CNT,SEG_BUF1,SEG_BUF2,SEG_BUF3,SEG_BUF4,SEG_BUF5,SEG_BUF6,SEG_BUF7,SEG_BUF8)
         BEGIN 
            CASE SEG_CNT IS
                WHEN "000" =>  SEG_TEMP<=SEG_BUF1;
                WHEN "001" =>  SEG_TEMP<=SEG_BUF2;
                WHEN "010" =>  SEG_TEMP<=SEG_BUF3;
                WHEN "011" =>  SEG_TEMP<=SEG_BUF4;
                WHEN "100" =>  SEG_TEMP<=SEG_BUF5;
                WHEN "101" =>  SEG_TEMP<=SEG_BUF6;
                WHEN "110" =>  SEG_TEMP<=SEG_BUF7;
                WHEN "111" =>  SEG_TEMP<=SEG_BUF8;
                WHEN OTHERS => NULL;
              END CASE;
           END PROCESS;
       PROCESS (SEG_TEMP)
          BEGIN
             CASE SEG_TEMP IS
                WHEN "0000" =>  SEG_DA<=x"3F";
                WHEN "0001" =>  SEG_DA<=x"06";
                WHEN "0010" =>  SEG_DA<=x"5B";
                WHEN "0011" =>  SEG_DA<=x"4F";
                WHEN "0100" =>  SEG_DA<=x"66";
                WHEN "0101" =>  SEG_DA<=x"6D";
                WHEN "0110" =>  SEG_DA<=x"7D";
                WHEN "0111" =>  SEG_DA<=x"07";
                WHEN "1000" =>  SEG_DA<=x"7F";
                WHEN "1001" =>  SEG_DA<=x"6F";
                WHEN "1010" =>  SEG_DA<=x"77";
                WHEN "1011" =>  SEG_DA<=x"7B";
                WHEN "1100" =>  SEG_DA<=x"39";
                WHEN "1101" =>  SEG_DA<=x"3E";
                WHEN "1110" =>  SEG_DA<=x"79";
                WHEN "1111" =>  SEG_DA<=x"00";
            END CASE;
         END PROCESS;
 U1 : CNT10 PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF1,COUT=>COUT(0),CIN=>'1');
 U2 : CNT6  PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF2,COUT=>COUT(1),CIN=>COUT(0));
 U3 : CNT10 PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF4,COUT=>COUT(2),CIN=>COUT(1));
 U4 : CNT6  PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF5,COUT=>COUT(3),CIN=>COUT(2));
 U5 : CNT4 PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF7,COUT=>COUT(4),CIN=>COUT(3));
 U6 : CNT2  PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF8,COUT=>COUT(5),CIN=>COUT(4));
 END ADO;

                
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY CNT10 IS
  PORT(CLK :IN STD_LOGIC;
       RST :IN STD_LOGIC;
       CIN :IN STD_LOGIC;
    CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       COUT:OUT STD_LOGIC
        );
END CNT10;
 
--ARCHITECTURE ADO1 OF CNT10 IS
--SIGNAL CNT_T :STD_LOGIC_VECTOR (3 DOWNTO 0);
--    BEGIN
--        PROCESS(CLK,RST)
--           BEGIN
--                   IF CLK'EVENT AND CLK='1' THEN 
--                       IF  RST='1' THEN 
--                           CNT_T <="0000";
--                       		IF  CIN='1'  THEN
--                            	IF CNT_T>"1001" THEN
---                             		CNT_T<="0000";
--                           	ELSE
--                             		CNT_T<=CNT_T+1;
---                            	END IF;
--                       		ELSE 
--                        		CNT_T<=CNT_T;
--                       		END IF;
--                       END IF;
--                   END IF;
--           END PROCESS;
--    COUT<='1' WHEN CNT_T=x"9" ELSE '0';
--    CNT_VAL<=CNT_T;-
--    END ADO1

ARCHITECTURE BEHAVE OF CNT10 IS
SIGNAL CNT_T:STD_LOGIC_VECTOR(3 DOWNTO 0);
    BEGIN 
       PROCESS(CLK)
         BEGIN 
              IF RST='1' THEN
                     CNT_T<="0000";
                 ELSIF CLK'EVENT AND CLK='1' THEN
                        IF CIN='1' THEN
                             IF CNT_T/= 9 THEN
                               CNT_T<=CNT_T+1;
                             ELSE 
                               CNT_T<="0000";
                             END IF;
                         END IF;
                  ELSE 
                       CNT_T<=CNT_T;
                  END IF;
           END PROCESS;
      COUT<='1' WHEN CNT_T=9 AND CIN='1' ELSE '0' ;
      CNT_VAL<=CNT_T;
      END BEHAVE;
     
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY cnt6 IS
 PORT(CLK :IN STD_LOGIC;
      RST :IN STD_LOGIC;
      CIN :IN STD_LOGIC;
   CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COUT:OUT STD_LOGIC      
    );
END CNT6;
 

ARCHITECTURE ADO2 OF CNT6 IS
SIGNAL CNT_T :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUTD :STD_LOGIC;
     BEGIN 
      PROCESS (CLK,RST)
           BEGIN
               IF  RST='1' THEN
                        CNT_T<="0000";
                  ELSIF CLK'EVENT AND CLK='1' THEN
                          IF   CIN='1' THEN
                               IF CNT_T< 5 THEN
                                 CNT_T<=CNT_T+1;
                                ELSE 
                                 CNT_T<=x"0";
                                END IF;
                            END IF;
                   ELSE
                         CNT_T<=CNT_T;
                END IF;
             END PROCESS;
     COUT<='1' WHEN CNT_T=5 AND CIN='1' ELSE '0';
     CNT_VAL<=CNT_T;
     END  ADO2;            


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY CNT2  IS
 PORT(CLK :IN STD_LOGIC;
      RST :IN STD_LOGIC;
       CIN:IN STD_LOGIC;
   CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COUT:OUT STD_LOGIC
        );
 END CNT2;

ARCHITECTURE ADO3 OF CNT2 IS
SIGNAL CNT_T:STD_LOGIC_VECTOR (3 DOWNTO 0);
      BEGIN 
        PROCESS(CLK,RST)
             BEGIN
               IF RST='1' THEN
                      	CNT_T<="0000";
                     ELSIF CLK'EVENT AND CLK='1' THEN
                        IF  CIN='1' THEN
                            IF CNT_T<1 THEN 
                              CNT_T<=CNT_T+1;
                            ELSE 
                              CNT_T<="0000";
                            END IF;
                          END IF;
                     ELSE 
                        CNT_T<=CNT_T;
                 END IF;
       END PROCESS;
     COUT<='1' WHEN CNT_T=1 AND CIN='1' ELSE '0';
     CNT_VAL<=CNT_T;
  END ADO3;
         
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY CNT4 IS
  PORT(CLK :IN STD_LOGIC;
       RST:IN STD_LOGIC;
       CIN:IN STD_LOGIC;
   CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COUT:OUT STD_LOGIC
       );
END CNT4;

ARCHITECTURE BEHAVE OF CNT4 IS
  SIGNAL CNT_T:STD_LOGIC_VECTOR(3 DOWNTO 0);
    BEGIN
       PROCESS(CLK,RST)
        BEGIN
            IF RST='1' THEN
                 CNT_T<="0000";
                ELSIF CLK'EVENT AND CLK='1' THEN
                      IF CIN='1' THEN
                          IF CNT_T<3 THEN
                             CNT_T<=CNT_T+1;
                          ELSE 
                             CNT_T<="0000";
                          END IF;
                      END IF;
                   ELSE
                   CNT_T<=CNT_T;
               END IF;
        END PROCESS;
       CNT_VAL<=CNT_T;
       COUT<='1' WHEN CNT_T=3 AND CIN='1' ELSE '0';
    END BEHAVE;

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -