ripple_carry_adder.v

来自「Verilog hdl语言 常用加法器设计」· Verilog 代码 · 共 22 行

// 二进制行波进位加法器
module ripple_carry_adder(x, y, cin, sum, cout);
	parameter	N = 8;
	input			cin;
	input  [N-1:0] 	x, y;
	output [N-1:0]	sum;
	output			cout;

	reg	cout;
	reg [N-1:0]	sum;
	reg  q[N:0];
	always @(x or y or cin)begin:ADDER
		integer i;
		q[0] = cin;
		for(i=0; i<=N-1; i=i+1)begin
			q[i+1] = (x[i]&y[i]) | (x[i]&q[i]) | (y[i]&q[i]);
			sum[i] = x[i] ^ y[i] ^ q[i];
		end
		cout = q[N];
	end
endmodule