carry_chain_adder.v

来自「Verilog hdl语言 常用加法器设计」· Verilog 代码 · 共 21 行

module carry_chain_adder(x, y, cin, sum, cout);
	parameter	DSIZE = 8;
	input				cin;
	input  [DSIZE-1:0] 	x, y;
	output [DSIZE-1:0]	sum;
	output				cout;
	reg	cout, q[DSIZE:0], p[DSIZE-1:0], g[DSIZE-1:0];
	reg [DSIZE-1:0]	sum;
	always @(x or y or cin)begin:ADDER
		integer i;
		q[0] = cin;
		for(i=0; i<DSIZE; i=i+1)begin
			p[i] = x[i]^y[i];
			g[i] = y[i];
			q[i+1] = (p[i])?q[i]:g[i];
			sum[i] = p[i]^q[i];
		end
		cout = q[DSIZE];
	end
endmodule