_primary.vhd

来自「简单使用的UART通信模块」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity send is
    port(
        rst             : in     vl_logic;
        flag            : in     vl_logic;
        clkin           : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        tdo             : out    vl_logic
    );
end send;