barker.vhd

《CPLD_FPGA设计及应用》课件与实例

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity barker is 
  port(clk,codein:in std_logic;
       q:out std_logic_vector(6 downto 0));
end barker;

architecture recogbk of barker is 
  signal temp:std_logic_vector(6 downto 0);
begin
  process(clk)
  begin
    if (clk'event and clk='1') then
       temp(6)<=codein;
       for i in 1 to 6 loop
         temp(6-i)<=temp(7-i);
       end loop;
    end if;
  end process;
      -- q(6)<=temp(6);
      -- q(5)<=temp(5);
      -- q(4)<=temp(4);
      -- q(3)<=not temp(3);
      -- q(2)<=not temp(2);
      -- q(1)<=temp(1);
      -- q(0)<=not temp(0);
  q<=temp(6)&temp(5)&temp(4)&(not temp(3))&(not temp(2))&temp(1)&(not temp(0));
end recogbk;