bitstd.fit.eqn

来自「《CPLD_FPGA设计及应用》课件与实例」· EQN 代码 · 共 32 行

--inst is inst at LC1_A9
--operation mode is normal

inst_lut_out = din;
inst = DFFEA(inst_lut_out, GLOBAL(clk), , , , , );


--inst1 is inst1 at LC3_A9
--operation mode is normal

inst1 = inst $ din;


--din is din at PIN_B9
--operation mode is input

din = INPUT();


--clk is clk at PIN_L8
--operation mode is input

clk = INPUT();


--out is out at PIN_E2
--operation mode is output

out = OUTPUT(inst1);