top.vhd

《CPLD_FPGA设计及应用》课件与实例

--计数器模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY countern IS
GENERIC(N:INTEGER:=16);
PORT(clr,ena,clk :in STD_LOGIC;
         q: BUFFER INTEGER RANGE 0 TO n-1 ;   --输出顺序地址
         cout: OUT STD_LOGIC );                --进位信号
END countern;
ARCHITECTURE rtl OF countern IS
BEGIN
  PROCESS(clk,clr)
BEGIN
IF clr='1' THEN
    q<=0;
  ELSE 
       IF clk='1' AND clk'EVENT  THEN
          IF ena='1' THEN
            IF q=q'high THEN
                q<=0;
        ELSE 
              q<=q+1;
        END IF;
      END IF;
     END IF;
END IF;
IF q=q'high THEN
      cout<='1';
  ELSE
      cout<='0';
END IF;
END PROCESS;
END rtl;

--选择器模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux2 IS
GENERIC(N:INTEGER:=16);
  port(d0: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      d1:IN INTEGER RANGE 0 TO N-1;
      SEL:IN STD_LOGIC;
      yout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END mux2;
ARCHITECTURE if_march OF mux2 is
BEGIN 
  PROCESS(d0,d1,sel)
  BEGIN
    IF(sel='1')THEN
   yout<=CONV_STD_LOGIC_VECTOR(d1,8);
    ELSE 
   yout<=d0;
END IF;
END PROCESS;
END if_march;

--只读存储器ROM模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY rom_16_8 is
GENERIC(N:INTEGER:=16);
PORT( addr : IN INTEGER RANGE 0 TO N-1;
          clk: IN STD_LOGIC;
          data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rom_16_8;
ARCHITECTURE rtl OF rom_16_8 IS
 SUBTYPE rom_word IS STD_LOGIC_VECTOR(7 DOWNTO 0);
 TYPE rom_table IS ARRAY(0 TO 15)OF rom_word;
  CONSTANt rom:rom_table:=rom_table'(
  rom_word'("00000000"),
  rom_word'("00000100"),  
  rom_word'("00001000"),
  rom_word'("00001100"),
  rom_word'("00000001"),
  rom_word'("00000101"),
  rom_word'("00001001"),
  rom_word'("00001101"),
  rom_word'("00000010"),
  rom_word'("00000110"),
  rom_word'("00001010"),
  rom_word'("00001110"),
  rom_word'("00000011"),
  rom_word'("00000111"),
  rom_word'("00001011"), 
  rom_word'("00001111")
);
BEGIN   
PROCESS(clk)
BEGIN
      IF clk'EVENT AND clk='1' THEN
         data<=rom(addr);
END IF;
END PROCESS;
END rtl;

--读写存储器RAM模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ram_16_8 IS
PORT(ad:IN STD_LOGIC_VECTOR(7 DOWNTO 0); --地址线，用来选择读和写单元地址
     clk:IN STD_LOGIC;
     di:IN STD_LOGIC_VECTOR(7 DOWNTO 0);     --输入数据
     do:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);    --输出数据
     wr_en: IN  STD_LOGIC:='0';              --写信号
     rd_en: IN  STD_LOGIC:='0');             --读信号
END ram_16_8;
ARCHITECTURE rtl OF ram_16_8 IS
SUBTYPE ram_word IS STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE ram_table IS ARRAY(0 TO 15)  OF  ram_word;
SIGNAL ram:ram_table:=ram_table'(
ram_word'("00000000"),
ram_word'("00000000"),  
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"),
ram_word'("00000000"), 
ram_word'("00000000"));
BEGIN
  PROCESS(clk)
   BEGIN
     IF clk'EVENT AND clk='1' THEN
        IF rd_en='1' THEN
        do<=ram(CONV_INTEGER(ad));
        END IF;
        IF wr_en='1' THEN
 ram(CONV_INTEGER(ad))<=di;
        END IF;
END IF;
END PROCESS;
END rtl;

--交织器顶层模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY top IS
GENERIC(N:INTEGER:=16);
PORT (clk: IN STD_LOGIC;
      clr: IN STD_LOGIC;
      ena: IN STD_LOGIC;
      di: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
do: OUT STD_LOGIC_VECTOR(7 DOWNTO 0););
END top;
ARCHITECTURE rtl OF top IS
COMPONENT countern
PORT(clr,ena,clk :IN STD_LOGIC;
     q: BUFFER INTEGER RANGE 0 TO N-1 :=0;
        cout: OUT STD_LOGIC );
END COMPONENT;
COMPONENT ROM_16_8
PORT(addr : IN INTEGER RANGE 0 TO N-1;
       clk: IN STD_LOGIC;
       data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT mux2
PORT( d0: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        d1:IN INTEGER RANGE 0 TO N-1;
        sel:IN STD_LOGIC;
yout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT ram_16_8
PORT(ad:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        clk:IN STD_LOGIC;
        di: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        do:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en: IN STD_LOGIC:='0';
rd_en: IN STD_LOGIC:='0');
END COMPONENT;
SIGNAL qs:INTEGER RANGE 0 TO N-1:=0;
SIGNAL ds:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ys:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cout: STD_LOGIC;
SIGNAL wr_en:STD_LOGIC:='0';
SIGNAL rd_en:STD_LOGIC:='0';
SIGNAL sel: STD_LOGIC:='1';
BEGIN
ct:countern
PORT MAP(clk=>clk,
                  clr=>clr,
ena=>ena,
                  cout=>cout,
                  q=>qs);
rom:ROM_16_8
PORT MAP(clk=>clk,
                  addr=>qs,
                  data=>ds);
mux:mux2
PORT MAP(d1=>qs,
         d0=>ds,
         sel=>sel,
         yout=>ys);
ram:ram_16_8
PORT MAP(clk=>clk,
         do=>do,
         di=>di,
         wr_en=>wr_en,
         rd_en=>rd_en,
         ad=>ys);
PROCESS(cout)
BEGIN
   IF cout'EVENT AND  cout='0' THEN
    sel<=NOT sel;
   END IF;
   IF sel='1' THEN
     wr_en<='1';
           ELSE
    rd_en<='1'; 
   END IF;
END PROCESS;
END rtl;