iirno.map.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 20 23:01:53 2006 " "Info: Processing started: Thu Apr 20 23:01:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off iirno -c iirno --generate_functional_sim_netlist " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off iirno -c iirno --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "iirno.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file iirno.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 iirno-iirnox " "Info: Found design unit 1: iirno-iirnox" {  } { { "D:/lizi/designiira/iirno.vhd" "iirno-iirnox" "" { Text "D:/lizi/designiira/iirno.vhd" 29 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 iirno " "Info: Found entity 1: iirno" {  } { { "D:/lizi/designiira/iirno.vhd" "iirno" "" { Text "D:/lizi/designiira/iirno.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clken iirno.vhd(87) " "Warning: VHDL Process Statement warning at iirno.vhd(87): signal clken is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter iirno.vhd(88) " "Warning: VHDL Process Statement warning at iirno.vhd(88): signal counter is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 88 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counterbt iirno.vhd(89) " "Warning: VHDL Process Statement warning at iirno.vhd(89): signal counterbt is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "suma iirno.vhd(102) " "Warning: VHDL Process Statement warning at iirno.vhd(102): signal suma is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "datayna iirno.vhd(106) " "Warning: VHDL Process Statement warning at iirno.vhd(106): signal datayna is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 106 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "resulta iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal resulta is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn0a iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn0a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn1a iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn1a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn2a iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn2a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addyn0a iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal addyn0a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addyn1a iirno.vhd(109) " "Warning: VHDL Process Statement warning at iirno.vhd(109): signal addyn1a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "suma iirno.vhd(116) " "Warning: VHDL Process Statement warning at iirno.vhd(116): signal suma is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn0a iirno.vhd(123) " "Warning: VHDL Process Statement warning at iirno.vhd(123): signal addxn0a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn1a iirno.vhd(124) " "Warning: VHDL Process Statement warning at iirno.vhd(124): signal addxn1a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 124 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addxn2a iirno.vhd(125) " "Warning: VHDL Process Statement warning at iirno.vhd(125): signal addxn2a is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "resulta iirno.vhd(126) " "Warning: VHDL Process Statement warning at iirno.vhd(126): signal resulta is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 126 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "suma iirno.vhd(127) " "Warning: VHDL Process Statement warning at iirno.vhd(127): signal suma is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "datayna iirno.vhd(128) " "Warning: VHDL Process Statement warning at iirno.vhd(128): signal datayna is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "datayntempa iirno.vhd(129) " "Warning: VHDL Process Statement warning at iirno.vhd(129): signal datayntempa is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "datayna iirno.vhd(96) " "Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable datayna may not be assigned a new value in every possible path through the Process Statement. Signal or variable datayna holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "resulta iirno.vhd(96) " "Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable resulta may not be assigned a new value in every possible path through the Process Statement. Signal or variable resulta holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "suma iirno.vhd(96) " "Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable suma may not be assigned a new value in every possible path through the Process Statement. Signal or variable suma holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "datayntempa iirno.vhd(96) " "Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable datayntempa may not be assigned a new value in every possible path through the Process Statement. Signal or variable datayntempa holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clrsm iirno.vhd(133) " "Warning: VHDL Process Statement warning at iirno.vhd(133): signal clrsm is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 133 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clken iirno.vhd(189) " "Warning: VHDL Process Statement warning at iirno.vhd(189): signal clken is in statement, but is not in sensitivity list" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 189 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_mux.tdf" "lpm_mux" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_mux.tdf" 78 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_lpc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_lpc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_lpc " "Info: Found entity 1: mux_lpc" {  } { { "D:/lizi/designiira/db/mux_lpc.tdf" "mux_lpc" "" { Text "D:/lizi/designiira/db/mux_lpc.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 20 23:01:55 2006 " "Info: Processing ended: Thu Apr 20 23:01:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}