iirno.tan.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 6 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clken " "Info: Detected ripple clock clken as buffer" {  } { { "D:/lizi/designiira/iirno.vhd" "" "" { Text "D:/lizi/designiira/iirno.vhd" 63 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clken" } } } }  } 0}  } {  } 0}