floor_select.tan.qmsg

《Verilog HDL数字控制系统设计实例》-冼进-源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 07 12:47:50 2006 " "Info: Processing started: Mon Aug 07 12:47:50 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Floor_Select -c Floor_Select " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Floor_Select -c Floor_Select" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "now_floor\[3\] floor_arrive 7.000 ns Longest " "Info: Longest tpd from source pin \"now_floor\[3\]\" to destination pin \"floor_arrive\" is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns now_floor\[3\] 1 PIN PIN_58 9 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_58; Fanout = 9; PIN Node = 'now_floor\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" Compiler "Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/" "" "" { now_floor[3] } "NODE_NAME" } "" } } { "Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/Floor_Select.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.600 ns floor_arrive~167 2 COMB LC2 1 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 1; COMB Node = 'floor_arrive~167'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" Compiler "Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/" "" "4.400 ns" { now_floor[3] floor_arrive~167 } "NODE_NAME" } "" } } { "Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/Floor_Select.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 6.600 ns floor_arrive~166 3 COMB LC3 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 6.600 ns; Loc. = LC3; Fanout = 1; COMB Node = 'floor_arrive~166'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" Compiler "Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/" "" "2.000 ns" { floor_arrive~167 floor_arrive~166 } "NODE_NAME" } "" } } { "Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/Floor_Select.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 7.000 ns floor_arrive 4 PIN PIN_10 0 " "Info: 4: + IC(0.000 ns) + CELL(0.400 ns) = 7.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'floor_arrive'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" Compiler "Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/" "" "0.400 ns" { floor_arrive~166 floor_arrive } "NODE_NAME" } "" } } { "Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/Floor_Select.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns 77.14 % " "Info: Total cell delay = 5.400 ns ( 77.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 22.86 % " "Info: Total interconnect delay = 1.600 ns ( 22.86 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select_cmp.qrpt" Compiler "Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/db/Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Floor_Select/" "" "7.000 ns" { now_floor[3] floor_arrive~167 floor_arrive~166 floor_arrive } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "7.000 ns" { now_floor[3] now_floor[3]~out floor_arrive~167 floor_arrive~166 floor_arrive } { 0.000ns 0.000ns 1.600ns 0.000ns 0.000ns } { 0.000ns 0.200ns 2.800ns 2.000ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 12:47:51 2006 " "Info: Processing ended: Mon Aug 07 12:47:51 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}