date_main.sim.qmsg

来自「《Verilog HDL数字控制系统设计实例》-冼进-源代码」· QMSG 代码 · 共 7 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 20:27:09 2006 " "Info: Processing started: Thu Jul 13 20:27:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off date_main -c date_main " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off date_main -c date_main" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     57.58 % " "Info: Simulation coverage is      57.58 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "747 " "Info: Number of transitions in simulation is 747" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 20:27:10 2006 " "Info: Processing ended: Thu Jul 13 20:27:10 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}