setdate.tan.qmsg

《Verilog HDL数字控制系统设计实例》-冼进-源代码

{ "Info" "ITDB_TSU_RESULT" "disp_drive\[0\]~reg0 EN2 SW1 3.300 ns register " "Info: tsu for register \"disp_drive\[0\]~reg0\" (data pin = \"EN2\", clock pin = \"SW1\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest pin register " "Info: + Longest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN2 1 PIN PIN_24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 2; PIN Node = 'EN2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { EN2 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns disp_drive\[0\]~reg0 2 REG LC6 15 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.800 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN2 EN2~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"SW1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW1 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW1 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns disp_drive\[0\]~reg0 2 REG LC6 15 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.800 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN2 EN2~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SW2 day_set0\[3\] lpm_counter:day_set0_rtl_3\|dffs\[3\] 2.800 ns register " "Info: tco from clock \"SW2\" to destination pin \"day_set0\[3\]\" through register \"lpm_counter:day_set0_rtl_3\|dffs\[3\]\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"SW2\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW2 1 CLK PIN_2 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW2 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:day_set0_rtl_3\|dffs\[3\] 2 REG LC2 8 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 8; REG Node = 'lpm_counter:day_set0_rtl_3\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW2 lpm_counter:day_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set0_rtl_3|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:day_set0_rtl_3\|dffs\[3\] 1 REG LC2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 8; REG Node = 'lpm_counter:day_set0_rtl_3\|dffs\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { lpm_counter:day_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns day_set0\[3\] 2 PIN PIN_5 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'day_set0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.200 ns" { lpm_counter:day_set0_rtl_3|dffs[3] day_set0[3] } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.200 ns" { lpm_counter:day_set0_rtl_3|dffs[3] day_set0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:day_set0_rtl_3|dffs[3] day_set0[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set0_rtl_3|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set0_rtl_3|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.200 ns" { lpm_counter:day_set0_rtl_3|dffs[3] day_set0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:day_set0_rtl_3|dffs[3] day_set0[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "disp_drive\[0\]~reg0 EN2 SW1 -0.800 ns register " "Info: th for register \"disp_drive\[0\]~reg0\" (data pin = \"EN2\", clock pin = \"SW1\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"SW1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW1 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW1 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns disp_drive\[0\]~reg0 2 REG LC6 15 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN2 1 PIN PIN_24 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 2; PIN Node = 'EN2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { EN2 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns disp_drive\[0\]~reg0 2 REG LC6 15 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.800 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN2 EN2~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.800 ns" { EN2 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { EN2 EN2~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 14:01:52 2006 " "Info: Processing ended: Thu Jul 13 14:01:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}