📄 setdate.tan.qmsg
字号:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register disp_drive\[0\]~reg0 register disp_drive\[1\]~reg0 175.44 MHz 5.7 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 175.44 MHz between source register \"disp_drive\[0\]~reg0\" and destination register \"disp_drive\[1\]~reg0\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns disp_drive\[0\]~reg0 1 REG LC6 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns disp_drive\[1\]~reg0 2 REG LC7 14 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC7; Fanout = 14; REG Node = 'disp_drive\[1\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { disp_drive[0]~reg0 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { disp_drive[0]~reg0 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { disp_drive[0]~reg0 disp_drive[1]~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW1 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW1 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns disp_drive\[1\]~reg0 2 REG LC7 14 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 14; REG Node = 'disp_drive\[1\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW1 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW1 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW1 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns disp_drive\[0\]~reg0 2 REG LC6 15 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive\[0\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 22 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { disp_drive[0]~reg0 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { disp_drive[0]~reg0 disp_drive[1]~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW1 disp_drive[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW1 SW1~out disp_drive[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register lpm_counter:day_set1_rtl_2\|dffs\[0\] register lpm_counter:day_set1_rtl_2\|dffs\[1\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 175.44 MHz between source register \"lpm_counter:day_set1_rtl_2\|dffs\[0\]\" and destination register \"lpm_counter:day_set1_rtl_2\|dffs\[1\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:day_set1_rtl_2\|dffs\[0\] 1 REG LC3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'lpm_counter:day_set1_rtl_2\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns lpm_counter:day_set1_rtl_2\|dffs\[1\] 2 REG LC12 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC12; Fanout = 2; REG Node = 'lpm_counter:day_set1_rtl_2\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { lpm_counter:day_set1_rtl_2|dffs[0] lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { lpm_counter:day_set1_rtl_2|dffs[0] lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:day_set1_rtl_2|dffs[0] lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW2 1 CLK PIN_2 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW2 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:day_set1_rtl_2\|dffs\[1\] 2 REG LC12 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC12; Fanout = 2; REG Node = 'lpm_counter:day_set1_rtl_2\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW2 1 CLK PIN_2 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "" { SW2 } "NODE_NAME" } "" } } { "setdate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/setdate.v" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:day_set1_rtl_2\|dffs\[0\] 2 REG LC3 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 3; REG Node = 'lpm_counter:day_set1_rtl_2\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "0.100 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "3.600 ns" { lpm_counter:day_set1_rtl_2|dffs[0] lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:day_set1_rtl_2|dffs[0] lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate_cmp.qrpt" Compiler "setdate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/db/setdate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/setdate/" "" "1.300 ns" { SW2 lpm_counter:day_set1_rtl_2|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW2 SW2~out lpm_counter:day_set1_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -