📄 timepiece_main.tan.qmsg
字号:
{ "Info" "ITDB_TSU_RESULT" "second_counter:b2v_inst2\|EO Timepiece_EN CLK 4.100 ns register " "Info: tsu for register \"second_counter:b2v_inst2\|EO\" (data pin = \"Timepiece_EN\", clock pin = \"CLK\") is 4.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Longest pin register " "Info: + Longest pin to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Timepiece_EN 1 PIN PIN_35 69 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 69; PIN Node = 'Timepiece_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { Timepiece_EN } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(2.600 ns) 4.200 ns second_counter:b2v_inst2\|LessThan~76 2 COMB LC42 1 " "Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC42; Fanout = 1; COMB Node = 'second_counter:b2v_inst2\|LessThan~76'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { Timepiece_EN second_counter:b2v_inst2|LessThan~76 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.100 ns second_counter:b2v_inst2\|EO 3 REG LC43 11 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.100 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.900 ns" { second_counter:b2v_inst2|LessThan~76 second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 72.55 % " "Info: Total cell delay = 3.700 ns ( 72.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 27.45 % " "Info: Total interconnect delay = 1.400 ns ( 27.45 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { Timepiece_EN second_counter:b2v_inst2|LessThan~76 second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Timepiece_EN Timepiece_EN~out second_counter:b2v_inst2|LessThan~76 second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 1.400ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns CLK 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { CLK } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns second_counter:b2v_inst2\|EO 2 REG LC43 11 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.500 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.800 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { Timepiece_EN second_counter:b2v_inst2|LessThan~76 second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Timepiece_EN Timepiece_EN~out second_counter:b2v_inst2|LessThan~76 second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 1.400ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.800 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out second_counter:b2v_inst2|EO } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK day_EN hour_counter:b2v_inst\|EO 13.500 ns register " "Info: tco from clock \"CLK\" to destination pin \"day_EN\" through register \"hour_counter:b2v_inst\|EO\" is 13.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.100 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns CLK 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { CLK } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.000 ns second_counter:b2v_inst2\|EO 2 REG LC43 11 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.700 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 8.100 ns minute_counter:b2v_inst1\|EO 3 REG LC27 10 " "Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(2.700 ns) 12.100 ns hour_counter:b2v_inst\|EO 4 REG LC46 4 " "Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns 79.34 % " "Info: Total cell delay = 9.600 ns ( 79.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 20.66 % " "Info: Total interconnect delay = 2.500 ns ( 20.66 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" { } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour_counter:b2v_inst\|EO 1 REG LC46 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns day_EN 2 PIN PIN_25 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'day_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.200 ns" { hour_counter:b2v_inst|EO day_EN } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.200 ns" { hour_counter:b2v_inst|EO day_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { hour_counter:b2v_inst|EO day_EN } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.200 ns" { hour_counter:b2v_inst|EO day_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { hour_counter:b2v_inst|EO day_EN } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\] Timepiece_EN CLK 9.600 ns register " "Info: th for register \"hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\]\" (data pin = \"Timepiece_EN\", clock pin = \"CLK\") is 9.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.100 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns CLK 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { CLK } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.000 ns second_counter:b2v_inst2\|EO 2 REG LC43 11 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.700 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 8.100 ns minute_counter:b2v_inst1\|EO 3 REG LC27 10 " "Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1\|EO'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(2.700 ns) 12.100 ns hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\] 4 REG LC36 18 " "Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC36; Fanout = 18; REG Node = 'hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns 79.34 % " "Info: Total cell delay = 9.600 ns ( 79.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 20.66 % " "Info: Total interconnect delay = 2.500 ns ( 20.66 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Timepiece_EN 1 PIN PIN_35 69 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_35; Fanout = 69; PIN Node = 'Timepiece_EN'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { Timepiece_EN } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(2.600 ns) 4.200 ns hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\] 2 REG LC36 18 " "Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC36; Fanout = 18; REG Node = 'hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { Timepiece_EN hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 66.67 % " "Info: Total cell delay = 2.800 ns ( 66.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 33.33 % " "Info: Total interconnect delay = 1.400 ns ( 33.33 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.200 ns" { Timepiece_EN hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Timepiece_EN Timepiece_EN~out hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 2.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.200 ns" { Timepiece_EN hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Timepiece_EN Timepiece_EN~out hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 2.600ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 17:07:47 2006 " "Info: Processing ended: Sat Jul 15 17:07:47 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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