timepiece_main.tan.qmsg

《Verilog HDL数字控制系统设计实例》-冼进-源代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "minute_counter:b2v_inst1\|EO " "Info: Detected ripple clock \"minute_counter:b2v_inst1\|EO\" as buffer" {  } { { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "minute_counter:b2v_inst1\|EO" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_counter:b2v_inst2\|EO " "Info: Detected ripple clock \"second_counter:b2v_inst2\|EO\" as buffer" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_counter:b2v_inst2\|EO" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\] register hour_counter:b2v_inst\|EO 149.25 MHz 6.7 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 149.25 MHz between source register \"hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\]\" and destination register \"hour_counter:b2v_inst\|EO\" (period= 6.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\] 1 REG LC53 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC53; Fanout = 23; REG Node = 'hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns hour_counter:b2v_inst\|EO~154 2 COMB LC45 1 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC45; Fanout = 1; COMB Node = 'hour_counter:b2v_inst\|EO~154'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "3.800 ns" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] hour_counter:b2v_inst|EO~154 } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.700 ns hour_counter:b2v_inst\|EO 3 REG LC46 4 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "0.900 ns" { hour_counter:b2v_inst|EO~154 hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 74.47 % " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 25.53 % " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.700 ns" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] hour_counter:b2v_inst|EO~154 hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] hour_counter:b2v_inst|EO~154 hour_counter:b2v_inst|EO } { 0.000ns 1.200ns 0.000ns } { 0.000ns 2.600ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.100 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns CLK 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { CLK } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.000 ns second_counter:b2v_inst2\|EO 2 REG LC43 11 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.700 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 8.100 ns minute_counter:b2v_inst1\|EO 3 REG LC27 10 " "Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(2.700 ns) 12.100 ns hour_counter:b2v_inst\|EO 4 REG LC46 4 " "Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC46; Fanout = 4; REG Node = 'hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns 79.34 % " "Info: Total cell delay = 9.600 ns ( 79.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 20.66 % " "Info: Total interconnect delay = 2.500 ns ( 20.66 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.100 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns CLK 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "" { CLK } "NODE_NAME" } "" } } { "timepiece_main.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/timepiece_main.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.000 ns second_counter:b2v_inst2\|EO 2 REG LC43 11 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.000 ns; Loc. = LC43; Fanout = 11; REG Node = 'second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "1.700 ns" { CLK second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 8.100 ns minute_counter:b2v_inst1\|EO 3 REG LC27 10 " "Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = LC27; Fanout = 10; REG Node = 'minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "5.100 ns" { second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(2.700 ns) 12.100 ns hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\] 4 REG LC53 23 " "Info: 4: + IC(1.300 ns) + CELL(2.700 ns) = 12.100 ns; Loc. = LC53; Fanout = 23; REG Node = 'hour_counter:b2v_inst\|lpm_counter:hour_data1_rtl_1\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.000 ns" { minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns 79.34 % " "Info: Total cell delay = 9.600 ns ( 79.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 20.66 % " "Info: Total interconnect delay = 2.500 ns ( 20.66 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/hour_counter.v" 4 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "4.700 ns" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] hour_counter:b2v_inst|EO~154 hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] hour_counter:b2v_inst|EO~154 hour_counter:b2v_inst|EO } { 0.000ns 1.200ns 0.000ns } { 0.000ns 2.600ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|EO } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main_cmp.qrpt" Compiler "timepiece_main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/db/timepiece_main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/timepiece_main/" "" "12.100 ns" { CLK second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "12.100 ns" { CLK CLK~out second_counter:b2v_inst2|EO minute_counter:b2v_inst1|EO hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_1|dffs[1] } { 0.000ns 0.000ns 0.000ns 1.200ns 1.300ns } { 0.000ns 1.300ns 1.700ns 3.900ns 2.700ns } } }  } 0}