timepiece_main.map.qmsg

来自「《Verilog HDL数字控制系统设计实例》-冼进-源代码」· QMSG 代码 · 共 3 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 17:08:16 2006 " "Info: Processing started: Sat Jul 15 17:08:16 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off timepiece_main -c timepiece_main --generate_symbol=E:\\戴仙金\\资料\\Verilog书\\源代码\\wristwatch\\timepiece\\timepiece_main\\timepiece_main.v " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off timepiece_main -c timepiece_main --generate_symbol=E:\\戴仙金\\资料\\Verilog书\\源代码\\wristwatch\\timepiece\\timepiece_main\\timepiece_main.v" {  } {  }