alu_test.v

来自「此代码能高速实算术逻辑单元的功能」· Verilog 代码 · 共 29 行

module alu_test;
    
reg clock;
reg ci;
reg [1:0]op;
reg [31:0]a,b;
wire [31:0]s;
wire n,v,c,z;

initial
   begin
        a=32'b0;
        b=32'b0;
        op=2'b0;
        clock=1'b0;
    end
    
    always #50clock=clock;
    always@(posedge clock)
       begin
           a={$random}%65535;
           b={$random}%65535;
           op={$random}%4;
           ci={$random}%2;
       end
       ALU alu(c32,s,op,a,b,ci,v,z,n);
       
   endmodule