qicheweideng.rpt

一个汽车尾灯的控制的程序

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:              e:\eda\qicheweideng\qicheweideng.rpt
qicheweideng

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC25 |LFTA:2|tmp2
        | +--------------------- LC24 |LFTA:2|tmp1
        | | +------------------- LC23 |LFTA:2|tmp0
        | | | +----------------- LC22 l0
        | | | | +--------------- LC20 l1
        | | | | | +------------- LC19 l2
        | | | | | | +----------- LC28 |RITA:3|tmp2
        | | | | | | | +--------- LC27 |RITA:3|tmp1
        | | | | | | | | +------- LC26 |RITA:3|tmp0
        | | | | | | | | | +----- LC17 r0
        | | | | | | | | | | +--- LC18 r1
        | | | | | | | | | | | +- LC21 r2
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - * - - * - - - - - - | - * | <-- |LFTA:2|tmp2
LC24 -> * - * - * - - - - - - - | - * | <-- |LFTA:2|tmp1
LC23 -> - * * * - - - - - - - - | - * | <-- |LFTA:2|tmp0
LC28 -> - - - - - - * * - - - * | - * | <-- |RITA:3|tmp2
LC27 -> - - - - - - * - * - * - | - * | <-- |RITA:3|tmp1
LC26 -> - - - - - - * - - * - - | - * | <-- |RITA:3|tmp0

Pin
43   -> - - - * * * - - - * * * | - * | <-- clk
4    -> * * * * * * * * * * * * | - * | <-- left
5    -> * * * * * * * * * * * * | - * | <-- right


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:              e:\eda\qicheweideng\qicheweideng.rpt
qicheweideng

** EQUATIONS **

clk      : INPUT;
left     : INPUT;
right    : INPUT;

-- Node name is 'l0' 
-- Equation name is 'l0', location is LC022, type is output.
 l0      = LCELL( _EQ001 $  _LC023);
  _EQ001 =  clk &  _LC023 &  left &  right;

-- Node name is 'l1' 
-- Equation name is 'l1', location is LC020, type is output.
 l1      = LCELL( _EQ002 $  _LC024);
  _EQ002 =  clk &  _LC024 &  left &  right;

-- Node name is 'l2' 
-- Equation name is 'l2', location is LC019, type is output.
 l2      = LCELL( _EQ003 $  _LC025);
  _EQ003 =  clk &  _LC025 &  left &  right;

-- Node name is 'r0' 
-- Equation name is 'r0', location is LC017, type is output.
 r0      = LCELL( _EQ004 $  _LC026);
  _EQ004 =  clk &  _LC026 &  left &  right;

-- Node name is 'r1' 
-- Equation name is 'r1', location is LC018, type is output.
 r1      = LCELL( _EQ005 $  _LC027);
  _EQ005 =  clk &  _LC027 &  left &  right;

-- Node name is 'r2' 
-- Equation name is 'r2', location is LC021, type is output.
 r2      = LCELL( _EQ006 $  _LC028);
  _EQ006 =  clk &  _LC028 &  left &  right;

-- Node name is '|LFTA:2|:13' = '|LFTA:2|tmp0' 
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( _EQ007 $  GND, GLOBAL( clk), !_EQ008, !_EQ009,  VCC);
  _EQ007 = !_LC023 & !_LC024 & !_LC025;
  _EQ008 = !left & !right;
  _EQ009 =  left &  right;

-- Node name is '|LFTA:2|:12' = '|LFTA:2|tmp1' 
-- Equation name is '_LC024', type is buried 
_LC024   = DFFE(!_LC023 $  VCC, GLOBAL( clk), !_EQ010, !_EQ011,  VCC);
  _EQ010 = !left & !right;
  _EQ011 =  left &  right;

-- Node name is '|LFTA:2|:11' = '|LFTA:2|tmp2' 
-- Equation name is '_LC025', type is buried 
_LC025   = DFFE(!_LC024 $  VCC, GLOBAL( clk), !_EQ012, !_EQ013,  VCC);
  _EQ012 = !left & !right;
  _EQ013 =  left &  right;

-- Node name is '|RITA:3|:13' = '|RITA:3|tmp0' 
-- Equation name is '_LC026', type is buried 
_LC026   = DFFE(!_LC027 $  VCC, GLOBAL( clk), !_EQ014, !_EQ015,  VCC);
  _EQ014 =  _X001;
  _X001  = EXP( left &  right);
  _EQ015 =  left &  right;

-- Node name is '|RITA:3|:12' = '|RITA:3|tmp1' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE(!_LC028 $  VCC, GLOBAL( clk), !_EQ016, !_EQ017,  VCC);
  _EQ016 =  _X001;
  _X001  = EXP( left &  right);
  _EQ017 =  left &  right;

-- Node name is '|RITA:3|:11' = '|RITA:3|tmp2' 
-- Equation name is '_LC028', type is buried 
_LC028   = DFFE( _EQ018 $  GND, GLOBAL( clk), !_EQ019, !_EQ020,  VCC);
  _EQ018 = !_LC026 & !_LC027 & !_LC028;
  _EQ019 =  _X001;
  _X001  = EXP( left &  right);
  _EQ020 =  left &  right;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                       e:\eda\qicheweideng\qicheweideng.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,285K