led_key.fit.rpt

FPGA EP2C5Q288C8 KEY操作 原码,测试OK 打开即用.

+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; |led_key                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 2    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |led_key            ; work         ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------+
; Delay Chain Summary                                                           ;
+------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+------+----------+---------------+---------------+-----------------------+-----+
; led1 ; Output   ; --            ; --            ; --                    ; --  ;
; key1 ; Input    ; 6             ; 6             ; --                    ; --  ;
+------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; key1                ;                   ;         ;
;      - led1         ; 0                 ; 6       ;
+---------------------+-------------------+---------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+------+--------------------------+
; Name ; Fan-Out                  ;
+------+--------------------------+
; key1 ; 1                        ;
+------+--------------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; Block interconnects        ; 1 / 15,666 ( < 1 % ) ;
; C16 interconnects          ; 1 / 812 ( < 1 % )    ;
; C4 interconnects           ; 1 / 11,424 ( < 1 % ) ;
; Direct links               ; 0 / 15,666 ( 0 % )   ;
; Global clocks              ; 0 / 8 ( 0 % )        ;
; Local interconnects        ; 0 / 4,608 ( 0 % )    ;
; R24 interconnects          ; 2 / 652 ( < 1 % )    ;
; R4 interconnects           ; 0 / 13,328 ( 0 % )   ;
+----------------------------+----------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; nCEO                                         ; Unreserved          ;
; ASDO,nCSO                                    ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 癈   ;
; High Junction Temperature ; 85 癈  ;
+---------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu May 29 21:56:13 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led_key -c led_key
Info: Selected device EP2C5Q208C8 for design "led_key"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 2 of 2 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5Q208I8 is compatible
    Info: Device EP2C8Q208C8 is compatible
    Info: Device EP2C8Q208I8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device res