sclock.sim.rpt

来自「FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.」· RPT 代码 · 共 332 行 · 第 1/5 页

; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On         ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      95.54 % ;
; Total nodes checked                                 ; 202          ;
; Total output ports checked                          ; 202          ;
; Total output ports with complete 1/0-value coverage ; 193          ;
; Total output ports with no 1/0-value coverage       ; 8            ;
; Total output ports with no 1-value coverage         ; 8            ;
; Total output ports with no 0-value coverage         ; 9            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                            ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                ; Output Port Name                                                                                                         ; Output Port Type ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------------+
; |counter|hcount[0]                                                                                                       ; |counter|hcount[0]                                                                                                       ; regout           ;
; |counter|mcount~0                                                                                                        ; |counter|mcount~0                                                                                                        ; out              ;
; |counter|mcount~1                                                                                                        ; |counter|mcount~1                                                                                                        ; out              ;
; |counter|mcount~2                                                                                                        ; |counter|mcount~2                                                                                                        ; out              ;
; |counter|mcount~3                                                                                                        ; |counter|mcount~3                                                                                                        ; out              ;
; |counter|mcount~4                                                                                                        ; |counter|mcount~4                                                                                                        ; out              ;
; |counter|mcount~5                                                                                                        ; |counter|mcount~5                                                                                                        ; out              ;
; |counter|hcount~0                                                                                                        ; |counter|hcount~0                                                                                                        ; out              ;
; |counter|hcount~1                                                                                                        ; |counter|hcount~1                                                                                                        ; out              ;
; |counter|hcount~2                                                                                                        ; |counter|hcount~2                                                                                                        ; out              ;
; |counter|hcount~3                                                                                                        ; |counter|hcount~3                                                                                                        ; out              ;
; |counter|scount~0                                                                                                        ; |counter|scount~0                                                                                                        ; out              ;
; |counter|scount~1                                                                                                        ; |counter|scount~1                                                                                                        ; out              ;
; |counter|scount~2                                                                                                        ; |counter|scount~2                                                                                                        ; out              ;
; |counter|scount~3                                                                                                        ; |counter|scount~3                                                                                                        ; out              ;
; |counter|scount~4                                                                                                        ; |counter|scount~4                                                                                                        ; out              ;
; |counter|scount~5                                                                                                        ; |counter|scount~5                                                                                                        ; out              ;
; |counter|scount[5]                                                                                                       ; |counter|scount[5]                                                                                                       ; regout           ;
; |counter|scount[4]                                                                                                       ; |counter|scount[4]                                                                                                       ; regout           ;
; |counter|scount[3]                                                                                                       ; |counter|scount[3]                                                                                                       ; regout           ;
; |counter|scount[2]                                                                                                       ; |counter|scount[2]                                                                                                       ; regout           ;
; |counter|scount[1]                                                                                                       ; |counter|scount[1]                                                                                                       ; regout           ;
; |counter|scount[0]                                                                                                       ; |counter|scount[0]                                                                                                       ; regout           ;