prev_cmp_sclock.tan.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Info" "ITDB_TSU_RESULT" "div:inst\|clk_out rst clk 5.747 ns register " "Info: tsu for register \"div:inst\|clk_out\" (data pin = \"rst\", clock pin = \"clk\") is 5.747 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.128 ns + Longest pin register " "Info: + Longest pin to register delay is 8.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns rst 1 PIN PIN_206 60 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 60; PIN Node = 'rst'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 168 -136 32 184 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.365 ns) + CELL(0.651 ns) 8.020 ns div:inst\|clk_out~80 2 COMB LCCOMB_X1_Y9_N6 1 " "Info: 2: + IC(6.365 ns) + CELL(0.651 ns) = 8.020 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'div:inst\|clk_out~80'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "7.016 ns" { rst div:inst|clk_out~80 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.128 ns div:inst\|clk_out 3 REG LCFF_X1_Y9_N7 6 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.128 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.763 ns ( 21.69 % ) " "Info: Total cell delay = 1.763 ns ( 21.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.365 ns ( 78.31 % ) " "Info: Total interconnect delay = 6.365 ns ( 78.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "8.128 ns" { rst div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "8.128 ns" { rst {} rst~combout {} div:inst|clk_out~80 {} div:inst|clk_out {} } { 0.000ns 0.000ns 6.365ns 0.000ns } { 0.000ns 1.004ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.341 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.535 ns) + CELL(0.666 ns) 2.341 ns div:inst\|clk_out 2 REG LCFF_X1_Y9_N7 6 " "Info: 2: + IC(0.535 ns) + CELL(0.666 ns) = 2.341 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.201 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 77.15 % ) " "Info: Total cell delay = 1.806 ns ( 77.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.535 ns ( 22.85 % ) " "Info: Total interconnect delay = 0.535 ns ( 22.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { clk {} clk~combout {} div:inst|clk_out {} } { 0.000ns 0.000ns 0.535ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "8.128 ns" { rst div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "8.128 ns" { rst {} rst~combout {} div:inst|clk_out~80 {} div:inst|clk_out {} } { 0.000ns 0.000ns 6.365ns 0.000ns } { 0.000ns 1.004ns 0.651ns 0.108ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { clk {} clk~combout {} div:inst|clk_out {} } { 0.000ns 0.000ns 0.535ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] counter:inst2\|scount\[3\] 27.543 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"counter:inst2\|scount\[3\]\" is 27.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.021 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.535 ns) + CELL(0.970 ns) 2.645 ns div:inst\|clk_out 2 REG LCFF_X1_Y9_N7 6 " "Info: 2: + IC(0.535 ns) + CELL(0.970 ns) = 2.645 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.000 ns) 3.460 ns div:inst\|clk_out~clkctrl 3 COMB CLKCTRL_G3 12 " "Info: 3: + IC(0.815 ns) + CELL(0.000 ns) = 3.460 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'div:inst\|clk_out~clkctrl'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { div:inst|clk_out div:inst|clk_out~clkctrl } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.666 ns) 5.021 ns counter:inst2\|scount\[3\] 4 REG LCFF_X22_Y12_N27 12 " "Info: 4: + IC(0.895 ns) + CELL(0.666 ns) = 5.021 ns; Loc. = LCFF_X22_Y12_N27; Fanout = 12; REG Node = 'counter:inst2\|scount\[3\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { div:inst|clk_out~clkctrl counter:inst2|scount[3] } "NODE_NAME" } } { "counter.v" "" { Text "E:/project/qii/sclock/counter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 55.29 % ) " "Info: Total cell delay = 2.776 ns ( 55.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.245 ns ( 44.71 % ) " "Info: Total interconnect delay = 2.245 ns ( 44.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "5.021 ns" { clk div:inst|clk_out div:inst|clk_out~clkctrl counter:inst2|scount[3] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "5.021 ns" { clk {} clk~combout {} div:inst|clk_out {} div:inst|clk_out~clkctrl {} counter:inst2|scount[3] {} } { 0.000ns 0.000ns 0.535ns 0.815ns 0.895ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "counter.v" "" { Text "E:/project/qii/sclock/counter.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.218 ns + Longest register pin " "Info: + Longest register to pin delay is 22.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst2\|scount\[3\] 1 REG LCFF_X22_Y12_N27 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y12_N27; Fanout = 12; REG Node = 'counter:inst2\|scount\[3\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter:inst2|scount[3] } "NODE_NAME" } } { "counter.v" "" { Text "E:/project/qii/sclock/counter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.141 ns) + CELL(0.621 ns) 1.762 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~11 2 COMB LCCOMB_X22_Y14_N22 2 " "Info: 2: + IC(1.141 ns) + CELL(0.621 ns) = 1.762 ns; Loc. = LCCOMB_X22_Y14_N22; Fanout = 2; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~11'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { counter:inst2|scount[3] counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.848 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~13 3 COMB LCCOMB_X22_Y14_N24 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.848 ns; Loc. = LCCOMB_X22_Y14_N24; Fanout = 2; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~13'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.934 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~15 4 COMB LCCOMB_X22_Y14_N26 1 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.934 ns; Loc. = LCCOMB_X22_Y14_N26; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~15'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.440 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~16 5 COMB LCCOMB_X22_Y14_N28 10 " "Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 2.440 ns; Loc. = LCCOMB_X22_Y14_N28; Fanout = 10; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~16'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.370 ns) 3.899 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[15\]~29 6 COMB LCCOMB_X22_Y13_N12 2 " "Info: 6: + IC(1.089 ns) + CELL(0.370 ns) = 3.899 ns; Loc. = LCCOMB_X22_Y13_N12; Fanout = 2; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[15\]~29'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.459 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.422 ns) + CELL(0.621 ns) 5.942 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[1\]~13 7 COMB LCCOMB_X22_Y14_N10 2 " "Info: 7: + IC(1.422 ns) + CELL(0.621 ns) = 5.942 ns; Loc. = LCCOMB_X22_Y14_N10; Fanout = 2; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[1\]~13'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 6.028 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[2\]~15 8 COMB LCCOMB_X22_Y14_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 6.028 ns; Loc. = LCCOMB_X22_Y14_N12; Fanout = 2; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[2\]~15'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 6.218 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[3\]~17 9 COMB LCCOMB_X22_Y14_N14 1 " "Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 6.218 ns; Loc. = LCCOMB_X22_Y14_N14; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[3\]~17'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 6.304 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[4\]~19 10 COMB LCCOMB_X22_Y14_N16 1 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 6.304 ns; Loc. = LCCOMB_X22_Y14_N16; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[4\]~19'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 6.810 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[5\]~20 11 COMB LCCOMB_X22_Y14_N18 8 " "Info: 11: + IC(0.000 ns) + CELL(0.506 ns) = 6.810 ns; Loc. = LCCOMB_X22_Y14_N18; Fanout = 8; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[5\]~20'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.651 ns) 8.168 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[23\]~511 12 COMB LCCOMB_X22_Y14_N6 1 " "Info: 12: + IC(0.707 ns) + CELL(0.651 ns) = 8.168 ns; Loc. = LCCOMB_X22_Y14_N6; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[23\]~511'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.358 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.621 ns) 9.500 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[4\]~19 13 COMB LCCOMB_X21_Y14_N22 1 " "Info: 13: + IC(0.711 ns) + CELL(0.621 ns) = 9.500 ns; Loc. = LCCOMB_X21_Y14_N22; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[4\]~19'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.332 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 52 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 10.006 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[5\]~20 14 COMB LCCOMB_X21_Y14_N24 3 " "Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 10.006 ns; Loc. = LCCOMB_X21_Y14_N24; Fanout = 3; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[5\]~20'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 52 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.366 ns) 10.766 ns counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[27\]~509 15 COMB LCCOMB_X21_Y14_N6 1 " "Info: 15: + IC(0.394 ns) + CELL(0.366 ns) = 10.766 ns; Loc. = LCCOMB_X21_Y14_N6; Fanout = 1; COMB Node = 'counter:inst2\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[27\]~509'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.760 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/sclock/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.490 ns) + CELL(0.650 ns) 12.906 ns segmain:inst1\|Mux1~13 16 COMB LCCOMB_X19_Y10_N30 1 " "Info: 16: + IC(1.490 ns) + CELL(0.650 ns) = 12.906 ns; Loc. = LCCOMB_X19_Y10_N30; Fanout = 1; COMB Node = 'segmain:inst1\|Mux1~13'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.140 ns" { counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 segmain:inst1|Mux1~13 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.042 ns) + CELL(0.651 ns) 14.599 ns segmain:inst1\|Mux1~14 17 COMB LCCOMB_X21_Y10_N6 7 " "Info: 17: + IC(1.042 ns) + CELL(0.651 ns) = 14.599 ns; Loc. = LCCOMB_X21_Y10_N6; Fanout = 7; COMB Node = 'segmain:inst1\|Mux1~14'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.693 ns" { segmain:inst1|Mux1~13 segmain:inst1|Mux1~14 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.651 ns) 15.688 ns segmain:inst1\|WideOr5~19 18 COMB LCCOMB_X21_Y10_N24 1 " "Info: 18: + IC(0.438 ns) + CELL(0.651 ns) = 15.688 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'segmain:inst1\|WideOr5~19'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.089 ns" { segmain:inst1|Mux1~14 segmain:inst1|WideOr5~19 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.424 ns) + CELL(3.106 ns) 22.218 ns seg_data\[1\] 19 PIN PIN_13 0 " "Info: 19: + IC(3.424 ns) + CELL(3.106 ns) = 22.218 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'seg_data\[1\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "6.530 ns" { segmain:inst1|WideOr5~19 seg_data[1] } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 224 720 896 240 "seg_data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.360 ns ( 46.63 % ) " "Info: Total cell delay = 10.360 ns ( 46.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.858 ns ( 53.37 % ) " "Info: Total interconnect delay = 11.858 ns ( 53.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "22.218 ns" { counter:inst2|scount[3] counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 segmain:inst1|Mux1~13 segmain:inst1|Mux1~14 segmain:inst1|WideOr5~19 seg_data[1] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "22.218 ns" { counter:inst2|scount[3] {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 {} segmain:inst1|Mux1~13 {} segmain:inst1|Mux1~14 {} segmain:inst1|WideOr5~19 {} seg_data[1] {} } { 0.000ns 1.141ns 0.000ns 0.000ns 0.000ns 1.089ns 1.422ns 0.000ns 0.000ns 0.000ns 0.000ns 0.707ns 0.711ns 0.000ns 0.394ns 1.490ns 1.042ns 0.438ns 3.424ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.506ns 0.370ns 0.621ns 0.086ns 0.190ns 0.086ns 0.506ns 0.651ns 0.621ns 0.506ns 0.366ns 0.650ns 0.651ns 0.651ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "5.021 ns" { clk div:inst|clk_out div:inst|clk_out~clkctrl counter:inst2|scount[3] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "5.021 ns" { clk {} clk~combout {} div:inst|clk_out {} div:inst|clk_out~clkctrl {} counter:inst2|scount[3] {} } { 0.000ns 0.000ns 0.535ns 0.815ns 0.895ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "22.218 ns" { counter:inst2|scount[3] counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 segmain:inst1|Mux1~13 segmain:inst1|Mux1~14 segmain:inst1|WideOr5~19 seg_data[1] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "22.218 ns" { counter:inst2|scount[3] {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[15]~29 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[1]~13 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[2]~15 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[3]~17 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~19 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~20 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[23]~511 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~19 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~20 {} counter:inst2|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[27]~509 {} segmain:inst1|Mux1~13 {} segmain:inst1|Mux1~14 {} segmain:inst1|WideOr5~19 {} seg_data[1] {} } { 0.000ns 1.141ns 0.000ns 0.000ns 0.000ns 1.089ns 1.422ns 0.000ns 0.000ns 0.000ns 0.000ns 0.707ns 0.711ns 0.000ns 0.394ns 1.490ns 1.042ns 0.438ns 3.424ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.506ns 0.370ns 0.621ns 0.086ns 0.190ns 0.086ns 0.506ns 0.651ns 0.621ns 0.506ns 0.366ns 0.650ns 0.651ns 0.651ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "segmain:inst1\|count\[13\] rst clk -4.297 ns register " "Info: th for register \"segmain:inst1\|count\[13\]\" (data pin = \"rst\", clock pin = \"clk\") is -4.297 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.860 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.666 ns) 2.860 ns segmain:inst1\|count\[13\] 3 REG LCFF_X1_Y15_N29 12 " "Info: 3: + IC(0.915 ns) + CELL(0.666 ns) = 2.860 ns; Loc. = LCFF_X1_Y15_N29; Fanout = 12; REG Node = 'segmain:inst1\|count\[13\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl segmain:inst1|count[13] } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.15 % ) " "Info: Total cell delay = 1.806 ns ( 63.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns ( 36.85 % ) " "Info: Total interconnect delay = 1.054 ns ( 36.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl segmain:inst1|count[13] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} segmain:inst1|count[13] {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.463 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns rst 1 PIN PIN_206 60 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 60; PIN Node = 'rst'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 168 -136 32 184 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.799 ns) + CELL(0.660 ns) 7.463 ns segmain:inst1\|count\[13\] 2 REG LCFF_X1_Y15_N29 12 " "Info: 2: + IC(5.799 ns) + CELL(0.660 ns) = 7.463 ns; Loc. = LCFF_X1_Y15_N29; Fanout = 12; REG Node = 'segmain:inst1\|count\[13\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "6.459 ns" { rst segmain:inst1|count[13] } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/sclock/segmain.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.664 ns ( 22.30 % ) " "Info: Total cell delay = 1.664 ns ( 22.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.799 ns ( 77.70 % ) " "Info: Total interconnect delay = 5.799 ns ( 77.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "7.463 ns" { rst segmain:inst1|count[13] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "7.463 ns" { rst {} rst~combout {} segmain:inst1|count[13] {} } { 0.000ns 0.000ns 5.799ns } { 0.000ns 1.004ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl segmain:inst1|count[13] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} segmain:inst1|count[13] {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "7.463 ns" { rst segmain:inst1|count[13] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "7.463 ns" { rst {} rst~combout {} segmain:inst1|count[13] {} } { 0.000ns 0.000ns 5.799ns } { 0.000ns 1.004ns 0.660ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}