sclock.hif

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

Version 7.2 Build 151 09/26/2007 SJ Full Version
11
920
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sclock
# storage
db|sclock.(0).cnf
db|sclock.(0).cnf
# case_insensitive
# source_file
sclock.bdf
a2d026482cdfeeffee877996ededd5
25
# internal_option {
BLOCK_DESIGN_NAMING
OFF
}
# hierarchies {
|
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
counter
# storage
db|sclock.(1).cnf
db|sclock.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
counter.v
57485e991c83d99de2fe757517f9ee96
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
counter:inst2
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
div
# storage
db|sclock.(2).cnf
db|sclock.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
div.v
b7b591e3cc2923cc1d596c6b83e3ec4e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
CLK_FREQ
00000010111110101111000010000000
PARAMETER_UNSIGNED_BIN
USR
DCLK_FREQ
00000000000000000000000000000010
PARAMETER_UNSIGNED_BIN
USR
}
# hierarchies {
div:inst
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
segmain
# storage
db|sclock.(3).cnf
db|sclock.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
segmain.v
63541d9740bf3eddadae4e829eb7242
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
segmain:inst1
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide
# storage
db|sclock.(4).cnf
db|sclock.(4).cnf
# case_insensitive
# source_file
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|lpm_divide.tdf
706ba3e8b43cbca887f6dcfbde4d7290
6
# user_parameter {
LPM_WIDTHN
6
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_vcm
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# include_file {
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_vcm
# storage
db|sclock.(5).cnf
db|sclock.(5).cnf
# case_insensitive
# source_file
db|lpm_divide_vcm.tdf
28c54751834f52aa7624161873dbbf4
6
# used_port {
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sign_div_unsign_9kh
# storage
db|sclock.(6).cnf
db|sclock.(6).cnf
# case_insensitive
# source_file
db|sign_div_unsign_9kh.tdf
7ad4f86d0e3104da02c863f9a56f81
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
alt_u_div_kve
# storage
db|sclock.(7).cnf
db|sclock.(7).cnf
# case_insensitive
# source_file
db|alt_u_div_kve.tdf
199bd85853783db4f6e37c7cd928b5
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_lkc
# storage
db|sclock.(8).cnf
db|sclock.(8).cnf
# case_insensitive
# source_file
db|add_sub_lkc.tdf
4390ca3a75177c3c2b3763ec2fb44dda
6
# used_port {
result0
-1
3
datab0
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_mkc
# storage
db|sclock.(9).cnf
db|sclock.(9).cnf
# case_insensitive
# source_file
db|add_sub_mkc.tdf
8e1b47b28ec4a47b2d4eb2ed14cf5c37
6
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide
# storage
db|sclock.(10).cnf
db|sclock.(10).cnf
# case_insensitive
# source_file
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|lpm_divide.tdf
706ba3e8b43cbca887f6dcfbde4d7290
6
# user_parameter {
LPM_WIDTHN
6
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_25m
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# include_file {
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
..|..|..|..|..|programfile|altera|q72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_25m
# storage
db|sclock.(11).cnf
db|sclock.(11).cnf
# case_insensitive
# source_file
db|lpm_divide_25m.tdf
6c732ede2b41a3d7155fa5e63abc838
6
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# lmf
..|..|..|..|..|programfile|altera|q72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete