sclock.hier_info

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

|sclock
beep <= counter:inst2.beep
rst => div:inst.rst_n
rst => counter:inst2.rst_n
rst => segmain:inst1.reset_n
clk => div:inst.clk_in
clk => segmain:inst1.clk
seg_com[0] <= segmain:inst1.seg_com[0]
seg_com[1] <= segmain:inst1.seg_com[1]
seg_com[2] <= segmain:inst1.seg_com[2]
seg_com[3] <= segmain:inst1.seg_com[3]
seg_data[0] <= segmain:inst1.seg_data[0]
seg_data[1] <= segmain:inst1.seg_data[1]
seg_data[2] <= segmain:inst1.seg_data[2]
seg_data[3] <= segmain:inst1.seg_data[3]
seg_data[4] <= segmain:inst1.seg_data[4]
seg_data[5] <= segmain:inst1.seg_data[5]
seg_data[6] <= segmain:inst1.seg_data[6]
seg_data[7] <= segmain:inst1.seg_data[7]
sled[0] <= counter:inst2.sled[0]
sled[1] <= counter:inst2.sled[1]
sled[2] <= counter:inst2.sled[2]
sled[3] <= counter:inst2.sled[3]


|sclock|counter:inst2
clk => scount[5].CLK
clk => scount[4].CLK
clk => scount[3].CLK
clk => scount[2].CLK
clk => scount[1].CLK
clk => scount[0].CLK
clk => mcount[5].CLK
clk => mcount[4].CLK
clk => mcount[3].CLK
clk => mcount[2].CLK
clk => mcount[1].CLK
clk => mcount[0].CLK
clk => sled[3].DATAIN
clk => sled[2].DATAIN
clk => sled[1].DATAIN
clk => sled[0].DATAIN
rst_n => scount[5].ACLR
rst_n => scount[4].ACLR
rst_n => scount[3].ACLR
rst_n => scount[2].ACLR
rst_n => scount[1].ACLR
rst_n => scount[0].ACLR
rst_n => mcount[5].ACLR
rst_n => mcount[4].ACLR
rst_n => mcount[3].ACLR
rst_n => mcount[2].ACLR
rst_n => mcount[1].ACLR
rst_n => mcount[0].ACLR
beep <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
sled[0] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[1] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[2] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[3] <= clk.DB_MAX_OUTPUT_PORT_TYPE
dataout[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[8] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[9] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[10] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[11] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[12] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[13] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[14] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[15] <= Div1.DB_MAX_OUTPUT_PORT_TYPE


|sclock|div:inst
rst_n => clk_div[31].ACLR
rst_n => clk_div[30].ACLR
rst_n => clk_div[29].ACLR
rst_n => clk_div[28].ACLR
rst_n => clk_div[27].ACLR
rst_n => clk_div[26].ACLR
rst_n => clk_div[25].ACLR
rst_n => clk_div[24].ACLR
rst_n => clk_div[23].ACLR
rst_n => clk_div[22].ACLR
rst_n => clk_div[21].ACLR
rst_n => clk_div[20].ACLR
rst_n => clk_div[19].ACLR
rst_n => clk_div[18].ACLR
rst_n => clk_div[17].ACLR
rst_n => clk_div[16].ACLR
rst_n => clk_div[15].ACLR
rst_n => clk_div[14].ACLR
rst_n => clk_div[13].ACLR
rst_n => clk_div[12].ACLR
rst_n => clk_div[11].ACLR
rst_n => clk_div[10].ACLR
rst_n => clk_div[9].ACLR
rst_n => clk_div[8].ACLR
rst_n => clk_div[7].ACLR
rst_n => clk_div[6].ACLR
rst_n => clk_div[5].ACLR
rst_n => clk_div[4].ACLR
rst_n => clk_div[3].ACLR
rst_n => clk_div[2].ACLR
rst_n => clk_div[1].ACLR
rst_n => clk_div[0].ACLR
rst_n => clk_out~reg0.ENA
clk_in => clk_div[31].CLK
clk_in => clk_div[30].CLK
clk_in => clk_div[29].CLK
clk_in => clk_div[28].CLK
clk_in => clk_div[27].CLK
clk_in => clk_div[26].CLK
clk_in => clk_div[25].CLK
clk_in => clk_div[24].CLK
clk_in => clk_div[23].CLK
clk_in => clk_div[22].CLK
clk_in => clk_div[21].CLK
clk_in => clk_div[20].CLK
clk_in => clk_div[19].CLK
clk_in => clk_div[18].CLK
clk_in => clk_div[17].CLK
clk_in => clk_div[16].CLK
clk_in => clk_div[15].CLK
clk_in => clk_div[14].CLK
clk_in => clk_div[13].CLK
clk_in => clk_div[12].CLK
clk_in => clk_div[11].CLK
clk_in => clk_div[10].CLK
clk_in => clk_div[9].CLK
clk_in => clk_div[8].CLK
clk_in => clk_div[7].CLK
clk_in => clk_div[6].CLK
clk_in => clk_div[5].CLK
clk_in => clk_div[4].CLK
clk_in => clk_div[3].CLK
clk_in => clk_div[2].CLK
clk_in => clk_div[1].CLK
clk_in => clk_div[0].CLK
clk_in => clk_out~reg0.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sclock|segmain:inst1
clk => count[36].CLK
clk => count[35].CLK
clk => count[34].CLK
clk => count[33].CLK
clk => count[32].CLK
clk => count[31].CLK
clk => count[30].CLK
clk => count[29].CLK
clk => count[28].CLK
clk => count[27].CLK
clk => count[26].CLK
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
reset_n => count~36.OUTPUTSELECT
reset_n => count~35.OUTPUTSELECT
reset_n => count~34.OUTPUTSELECT
reset_n => count~33.OUTPUTSELECT
reset_n => count~32.OUTPUTSELECT
reset_n => count~31.OUTPUTSELECT
reset_n => count~30.OUTPUTSELECT
reset_n => count~29.OUTPUTSELECT
reset_n => count~28.OUTPUTSELECT
reset_n => count~27.OUTPUTSELECT
reset_n => count~26.OUTPUTSELECT
reset_n => count~25.OUTPUTSELECT
reset_n => count~24.OUTPUTSELECT
reset_n => count~23.OUTPUTSELECT
reset_n => count~22.OUTPUTSELECT
reset_n => count~21.OUTPUTSELECT
reset_n => count~20.OUTPUTSELECT
reset_n => count~19.OUTPUTSELECT
reset_n => count~18.OUTPUTSELECT
reset_n => count~17.OUTPUTSELECT
reset_n => count~16.OUTPUTSELECT
reset_n => count~15.OUTPUTSELECT
reset_n => count~14.OUTPUTSELECT
reset_n => count~13.OUTPUTSELECT
reset_n => count~12.OUTPUTSELECT
reset_n => count~11.OUTPUTSELECT
reset_n => count~10.OUTPUTSELECT
reset_n => count~9.OUTPUTSELECT
reset_n => count~8.OUTPUTSELECT
reset_n => count~7.OUTPUTSELECT
reset_n => count~6.OUTPUTSELECT
reset_n => count~5.OUTPUTSELECT
reset_n => count~4.OUTPUTSELECT
reset_n => count~3.OUTPUTSELECT
reset_n => count~2.OUTPUTSELECT
reset_n => count~1.OUTPUTSELECT
reset_n => count~0.OUTPUTSELECT
datain[0] => Mux3.IN3
datain[1] => Mux2.IN3
datain[2] => Mux1.IN3
datain[3] => Mux0.IN3
datain[4] => Mux3.IN2
datain[5] => Mux2.IN2
datain[6] => Mux1.IN2
datain[7] => Mux0.IN2
datain[8] => Mux3.IN1
datain[9] => Mux2.IN1
datain[10] => Mux1.IN1
datain[11] => Mux0.IN1
datain[12] => Mux3.IN0
datain[13] => Mux2.IN0
datain[14] => Mux1.IN0
datain[15] => Mux0.IN0
seg_data[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
seg_data[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= <VCC>
seg_com[0] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE