prev_cmp_sclock.fit.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.161 ns register register " "Info: Estimated most critical path is register to register delay of 6.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst\|clk_div\[5\] 1 REG LAB_X2_Y9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y9; Fanout = 3; REG Node = 'div:inst\|clk_div\[5\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { div:inst|clk_div[5] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.206 ns) 1.187 ns div:inst\|LessThan0~460 2 COMB LAB_X1_Y9 1 " "Info: 2: + IC(0.981 ns) + CELL(0.206 ns) = 1.187 ns; Loc. = LAB_X1_Y9; Fanout = 1; COMB Node = 'div:inst\|LessThan0~460'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { div:inst|clk_div[5] div:inst|LessThan0~460 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 1.998 ns div:inst\|LessThan0~461 3 COMB LAB_X1_Y9 1 " "Info: 3: + IC(0.441 ns) + CELL(0.370 ns) = 1.998 ns; Loc. = LAB_X1_Y9; Fanout = 1; COMB Node = 'div:inst\|LessThan0~461'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { div:inst|LessThan0~460 div:inst|LessThan0~461 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 2.809 ns div:inst\|LessThan0~463 4 COMB LAB_X1_Y9 1 " "Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 2.809 ns; Loc. = LAB_X1_Y9; Fanout = 1; COMB Node = 'div:inst\|LessThan0~463'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { div:inst|LessThan0~461 div:inst|LessThan0~463 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 3.620 ns div:inst\|LessThan0~464 5 COMB LAB_X1_Y9 1 " "Info: 5: + IC(0.187 ns) + CELL(0.624 ns) = 3.620 ns; Loc. = LAB_X1_Y9; Fanout = 1; COMB Node = 'div:inst\|LessThan0~464'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { div:inst|LessThan0~463 div:inst|LessThan0~464 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.616 ns) 4.423 ns div:inst\|LessThan0~465 6 COMB LAB_X1_Y9 33 " "Info: 6: + IC(0.187 ns) + CELL(0.616 ns) = 4.423 ns; Loc. = LAB_X1_Y9; Fanout = 33; COMB Node = 'div:inst\|LessThan0~465'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { div:inst|LessThan0~464 div:inst|LessThan0~465 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.660 ns) 6.161 ns div:inst\|clk_div\[23\] 7 REG LAB_X2_Y8 3 " "Info: 7: + IC(1.078 ns) + CELL(0.660 ns) = 6.161 ns; Loc. = LAB_X2_Y8; Fanout = 3; REG Node = 'div:inst\|clk_div\[23\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { div:inst|LessThan0~465 div:inst|clk_div[23] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.127 ns ( 50.75 % ) " "Info: Total cell delay = 3.127 ns ( 50.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.034 ns ( 49.25 % ) " "Info: Total interconnect delay = 3.034 ns ( 49.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "6.161 ns" { div:inst|clk_div[5] div:inst|LessThan0~460 div:inst|LessThan0~461 div:inst|LessThan0~463 div:inst|LessThan0~464 div:inst|LessThan0~465 div:inst|clk_div[23] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X11_Y10 X22_Y19 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X11_Y10 to location X22_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "17 " "Warning: Found 17 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "beep 0 " "Info: Pin \"beep\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[3\] 0 " "Info: Pin \"seg_com\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[2\] 0 " "Info: Pin \"seg_com\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[1\] 0 " "Info: Pin \"seg_com\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[0\] 0 " "Info: Pin \"seg_com\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[7\] 0 " "Info: Pin \"seg_data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[6\] 0 " "Info: Pin \"seg_data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[5\] 0 " "Info: Pin \"seg_data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[4\] 0 " "Info: Pin \"seg_data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[3\] 0 " "Info: Pin \"seg_data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[2\] 0 " "Info: Pin \"seg_data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[1\] 0 " "Info: Pin \"seg_data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[0\] 0 " "Info: Pin \"seg_data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sled\[3\] 0 " "Info: Pin \"sled\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sled\[2\] 0 " "Info: Pin \"sled\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sled\[1\] 0 " "Info: Pin \"sled\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sled\[0\] 0 " "Info: Pin \"sled\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg_data\[7\] VCC " "Info: Pin seg_data\[7\] has VCC driving its datain port" {  } { { "e:/programfile/altera/q72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/programfile/altera/q72/quartus/bin/pin_planner.ppl" { seg_data[7] } } } { "e:/programfile/altera/q72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/q72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg_data\[7\]" } } } } { "sclock.bdf" "" { Schematic "E:/project/qii/sclock/sclock.bdf" { { 224 720 896 240 "seg_data\[7..0\]" "" } } } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[7] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/project/qii/sclock/sclock.fit.smsg " "Info: Generated suppressed messages file E:/project/qii/sclock/sclock.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Allocated 177 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 10 16:25:41 2008 " "Info: Processing ended: Tue Jun 10 16:25:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}