sclock.tan.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Info" "ITDB_TH_RESULT" "div:inst\|clk_out rst clk -4.500 ns register " "Info: th for register \"div:inst\|clk_out\" (data pin = \"rst\", clock pin = \"clk\") is -4.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.739 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.933 ns) + CELL(0.666 ns) 2.739 ns div:inst\|clk_out 2 REG LCFF_X1_Y5_N11 6 " "Info: 2: + IC(0.933 ns) + CELL(0.666 ns) = 2.739 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.94 % ) " "Info: Total cell delay = 1.806 ns ( 65.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.933 ns ( 34.06 % ) " "Info: Total interconnect delay = 0.933 ns ( 34.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.739 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.739 ns" { clk {} clk~combout {} div:inst|clk_out {} } { 0.000ns 0.000ns 0.933ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.545 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns rst 1 PIN PIN_206 60 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 60; PIN Node = 'rst'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 168 -136 32 184 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.227 ns) + CELL(0.206 ns) 7.437 ns div:inst\|clk_out~80 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.227 ns) + CELL(0.206 ns) = 7.437 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'div:inst\|clk_out~80'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "6.433 ns" { rst div:inst|clk_out~80 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.545 ns div:inst\|clk_out 3 REG LCFF_X1_Y5_N11 6 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.545 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.318 ns ( 17.47 % ) " "Info: Total cell delay = 1.318 ns ( 17.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.227 ns ( 82.53 % ) " "Info: Total interconnect delay = 6.227 ns ( 82.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "7.545 ns" { rst div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "7.545 ns" { rst {} rst~combout {} div:inst|clk_out~80 {} div:inst|clk_out {} } { 0.000ns 0.000ns 6.227ns 0.000ns } { 0.000ns 1.004ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.739 ns" { clk div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.739 ns" { clk {} clk~combout {} div:inst|clk_out {} } { 0.000ns 0.000ns 0.933ns } { 0.000ns 1.140ns 0.666ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "7.545 ns" { rst div:inst|clk_out~80 div:inst|clk_out } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "7.545 ns" { rst {} rst~combout {} div:inst|clk_out~80 {} div:inst|clk_out {} } { 0.000ns 0.000ns 6.227ns 0.000ns } { 0.000ns 1.004ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 10 16:28:42 2008 "