sclock.tan.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:inst\|clk_out " "Info: Detected ripple clock \"div:inst\|clk_out\" as buffer" {  } { { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 10 -1 0 } } { "e:/programfile/altera/q72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/q72/quartus/bin/Assignment Editor.qase" 1 { { 0 "div:inst\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div:inst\|clk_div\[7\] register div:inst\|clk_div\[24\] 169.72 MHz 5.892 ns Internal " "Info: Clock \"clk\" has Internal fmax of 169.72 MHz between source register \"div:inst\|clk_div\[7\]\" and destination register \"div:inst\|clk_div\[24\]\" (period= 5.892 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.632 ns + Longest register register " "Info: + Longest register to register delay is 5.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst\|clk_div\[7\] 1 REG LCFF_X2_Y5_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y5_N15; Fanout = 3; REG Node = 'div:inst\|clk_div\[7\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { div:inst|clk_div[7] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.534 ns) 1.561 ns div:inst\|LessThan0~458 2 COMB LCCOMB_X1_Y5_N14 1 " "Info: 2: + IC(1.027 ns) + CELL(0.534 ns) = 1.561 ns; Loc. = LCCOMB_X1_Y5_N14; Fanout = 1; COMB Node = 'div:inst\|LessThan0~458'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { div:inst|clk_div[7] div:inst|LessThan0~458 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.370 ns) 2.306 ns div:inst\|LessThan0~461 3 COMB LCCOMB_X1_Y5_N2 1 " "Info: 3: + IC(0.375 ns) + CELL(0.370 ns) = 2.306 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 1; COMB Node = 'div:inst\|LessThan0~461'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.745 ns" { div:inst|LessThan0~458 div:inst|LessThan0~461 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.206 ns) 2.870 ns div:inst\|LessThan0~463 4 COMB LCCOMB_X1_Y5_N0 1 " "Info: 4: + IC(0.358 ns) + CELL(0.206 ns) = 2.870 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'div:inst\|LessThan0~463'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { div:inst|LessThan0~461 div:inst|LessThan0~463 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.206 ns) 3.444 ns div:inst\|LessThan0~464 5 COMB LCCOMB_X1_Y5_N22 1 " "Info: 5: + IC(0.368 ns) + CELL(0.206 ns) = 3.444 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; COMB Node = 'div:inst\|LessThan0~464'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.574 ns" { div:inst|LessThan0~463 div:inst|LessThan0~464 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.206 ns) 4.009 ns div:inst\|LessThan0~465 6 COMB LCCOMB_X1_Y5_N16 33 " "Info: 6: + IC(0.359 ns) + CELL(0.206 ns) = 4.009 ns; Loc. = LCCOMB_X1_Y5_N16; Fanout = 33; COMB Node = 'div:inst\|LessThan0~465'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { div:inst|LessThan0~464 div:inst|LessThan0~465 } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.660 ns) 5.632 ns div:inst\|clk_div\[24\] 7 REG LCFF_X2_Y4_N17 3 " "Info: 7: + IC(0.963 ns) + CELL(0.660 ns) = 5.632 ns; Loc. = LCFF_X2_Y4_N17; Fanout = 3; REG Node = 'div:inst\|clk_div\[24\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { div:inst|LessThan0~465 div:inst|clk_div[24] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.182 ns ( 38.74 % ) " "Info: Total cell delay = 2.182 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.450 ns ( 61.26 % ) " "Info: Total interconnect delay = 3.450 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "5.632 ns" { div:inst|clk_div[7] div:inst|LessThan0~458 div:inst|LessThan0~461 div:inst|LessThan0~463 div:inst|LessThan0~464 div:inst|LessThan0~465 div:inst|clk_div[24] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "5.632 ns" { div:inst|clk_div[7] {} div:inst|LessThan0~458 {} div:inst|LessThan0~461 {} div:inst|LessThan0~463 {} div:inst|LessThan0~464 {} div:inst|LessThan0~465 {} div:inst|clk_div[24] {} } { 0.000ns 1.027ns 0.375ns 0.358ns 0.368ns 0.359ns 0.963ns } { 0.000ns 0.534ns 0.370ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.776 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 2.776 ns div:inst\|clk_div\[24\] 3 REG LCFF_X2_Y4_N17 3 " "Info: 3: + IC(0.827 ns) + CELL(0.666 ns) = 2.776 ns; Loc. = LCFF_X2_Y4_N17; Fanout = 3; REG Node = 'div:inst\|clk_div\[24\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk~clkctrl div:inst|clk_div[24] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.06 % ) " "Info: Total cell delay = 1.806 ns ( 65.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 34.94 % ) " "Info: Total interconnect delay = 0.970 ns ( 34.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { clk clk~clkctrl div:inst|clk_div[24] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[24] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.772 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 47 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 47; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 136 -136 32 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 2.772 ns div:inst\|clk_div\[7\] 3 REG LCFF_X2_Y5_N15 3 " "Info: 3: + IC(0.823 ns) + CELL(0.666 ns) = 2.772 ns; Loc. = LCFF_X2_Y5_N15; Fanout = 3; REG Node = 'div:inst\|clk_div\[7\]'" {  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl div:inst|clk_div[7] } "NODE_NAME" } } { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.15 % ) " "Info: Total cell delay = 1.806 ns ( 65.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.966 ns ( 34.85 % ) " "Info: Total interconnect delay = 0.966 ns ( 34.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl div:inst|clk_div[7] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[7] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { clk clk~clkctrl div:inst|clk_div[24] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[24] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl div:inst|clk_div[7] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[7] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "5.632 ns" { div:inst|clk_div[7] div:inst|LessThan0~458 div:inst|LessThan0~461 div:inst|LessThan0~463 div:inst|LessThan0~464 div:inst|LessThan0~465 div:inst|clk_div[24] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "5.632 ns" { div:inst|clk_div[7] {} div:inst|LessThan0~458 {} div:inst|LessThan0~461 {} div:inst|LessThan0~463 {} div:inst|LessThan0~464 {} div:inst|LessThan0~465 {} div:inst|clk_div[24] {} } { 0.000ns 1.027ns 0.375ns 0.358ns 0.368ns 0.359ns 0.963ns } { 0.000ns 0.534ns 0.370ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.776 ns" { clk clk~clkctrl div:inst|clk_div[24] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.776 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[24] {} } { 0.000ns 0.000ns 0.143ns 0.827ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/q72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl div:inst|clk_div[7] } "NODE_NAME" } } { "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/q72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} div:inst|clk_div[7] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}