sclock.map.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "sclock.bdf" "inst" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 200 104 224 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst1 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst1\"" {  } { { "sclock.bdf" "inst1" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 200 520 704 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Div0\"" {  } { { "counter.v" "Div0" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 14 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Mod1\"" {  } { { "counter.v" "Mod1" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 15 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Mod0\"" {  } { { "counter.v" "Mod0" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 13 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Div1\"" {  } { { "counter.v" "Div1" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 16 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../programfile/altera/q72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../programfile/altera/q72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/programfile/altera/q72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst2\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"counter:inst2\|lpm_divide:Div0\"" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 14 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_vcm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_vcm " "Info: Found entity 1: lpm_divide_vcm" {  } { { "db/lpm_divide_vcm.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/lpm_divide_vcm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Info: Found entity 1: sign_div_unsign_9kh" {  } { { "db/sign_div_unsign_9kh.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/sign_div_unsign_9kh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_kve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_kve " "Info: Found entity 1: alt_u_div_kve" {  } { { "db/alt_u_div_kve.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/alt_u_div_kve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst2\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"counter:inst2\|lpm_divide:Mod1\"" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 15 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_25m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_25m " "Info: Found entity 1: lpm_divide_25m" {  } { { "db/lpm_divide_25m.tdf" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/db/lpm_divide_25m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[7\] VCC " "Warning (13410): Pin \"seg_data\[7\]\" stuck at VCC" {  } { { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 224 720 896 240 "seg_data\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "22 22 " "Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[15\] " "Info: Register \"segmain:inst1\|count\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[16\] " "Info: Register \"segmain:inst1\|count\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[17\] " "Info: Register \"segmain:inst1\|count\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[18\] " "Info: Register \"segmain:inst1\|count\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[19\] " "Info: Register \"segmain:inst1\|count\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[20\] " "Info: Register \"segmain:inst1\|count\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[21\] " "Info: Register \"segmain:inst1\|count\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[22\] " "Info: Register \"segmain:inst1\|count\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[23\] " "Info: Register \"segmain:inst1\|count\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[24\] " "Info: Register \"segmain:inst1\|count\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[25\] " "Info: Register \"segmain:inst1\|count\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[26\] " "Info: Register \"segmain:inst1\|count\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[27\] " "Info: Register \"segmain:inst1\|count\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[28\] " "Info: Register \"segmain:inst1\|count\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[29\] " "Info: Register \"segmain:inst1\|count\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[30\] " "Info: Register \"segmain:inst1\|count\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[31\] " "Info: Register \"segmain:inst1\|count\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[32\] " "Info: Register \"segmain:inst1\|count\[32\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[33\] " "Info: Register \"segmain:inst1\|count\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[34\] " "Info: Register \"segmain:inst1\|count\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[35\] " "Info: Register \"segmain:inst1\|count\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[36\] " "Info: Register \"segmain:inst1\|count\[36\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.map.smsg " "Info: Generated suppressed messages file E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "238 " "Info: Implemented 238 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "219 " "Info: Implemented 219 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 10 16:28:25 2008 " "Info: Processing ended: Tue Jun 10 16:28:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}