sclock.map.qmsg

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 10 16:28:18 2008 " "Info: Processing started: Tue Jun 10 16:28:18 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sclock -c sclock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sclock -c sclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sclock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sclock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sclock " "Info: Found entity 1: sclock" {  } { { "sclock.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "segmain.v(14) " "Warning (10268): Verilog HDL information at segmain.v(14): Always Construct contains both blocking and non-blocking assignments" {  } { { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/segmain.v" 14 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div.v" { { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/div.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sclock " "Info: Elaborating entity \"sclock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst2 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst2\"" {  } { { "sclock.bdf" "inst2" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.bdf" { { 200 288 432 296 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(13) " "Warning (10230): Verilog HDL assignment warning at counter.v(13): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(14) " "Warning (10230): Verilog HDL assignment warning at counter.v(14): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(15) " "Warning (10230): Verilog HDL assignment warning at counter.v(15): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(16) " "Warning (10230): Verilog HDL assignment warning at counter.v(16): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 counter.v(17) " "Warning (10230): Verilog HDL assignment warning at counter.v(17): truncated value with size 32 to match size of target (1)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 counter.v(28) " "Warning (10230): Verilog HDL assignment warning at counter.v(28): truncated value with size 32 to match size of target (6)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 counter.v(32) " "Warning (10230): Verilog HDL assignment warning at counter.v(32): truncated value with size 32 to match size of target (6)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(38) " "Warning (10230): Verilog HDL assignment warning at counter.v(38): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/sclock/counter.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}