div.v

来自「FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.」· Verilog 代码 · 共 29 行

/************************************
*         www.daleda.com            *
************************************/
// output clock=DCLK_FREQ/2 HZ

module div(rst_n,clk_in,clk_out);
input clk_in;
input rst_n;

output reg clk_out;
reg [31:0] clk_div;

parameter CLK_FREQ = 'D50_000_000;           //input clock 50MHz
parameter DCLK_FREQ = 'D2;          //output clock DCLK_FREQ/2Hz

always @(posedge clk_in or negedge rst_n)
begin
	if(!rst_n)
	  clk_div<=0;
	else if(clk_div<(CLK_FREQ/DCLK_FREQ-1))
		clk_div <= clk_div + 1;
	else
		begin
			clk_div <= 0;
			clk_out <= ~clk_out;             //
		end
	end
endmodule