sclock.qsf

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		sclock_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY sclock
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:34:48  MAY 30, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name BDF_FILE sclock.bdf
set_global_assignment -name VERILOG_FILE segmain.v
set_global_assignment -name VERILOG_FILE div.v
set_global_assignment -name VERILOG_FILE counter.v
set_global_assignment -name VECTOR_WAVEFORM_FILE sclock.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name TCL_SCRIPT_FILE setup.tcl
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_23 -to clk
set_location_assignment PIN_206 -to rst
set_location_assignment PIN_11 -to seg_com[0]
set_location_assignment PIN_12 -to seg_com[1]
set_location_assignment PIN_8 -to seg_com[2]
set_location_assignment PIN_10 -to seg_com[3]
set_location_assignment PIN_15 -to seg_data[0]
set_location_assignment PIN_13 -to seg_data[1]
set_location_assignment PIN_34 -to seg_data[2]
set_location_assignment PIN_31 -to seg_data[3]
set_location_assignment PIN_30 -to seg_data[4]
set_location_assignment PIN_14 -to seg_data[5]
set_location_assignment PIN_35 -to seg_data[6]
set_location_assignment PIN_33 -to seg_data[7]
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_170 -to sled[0]
set_location_assignment PIN_171 -to sled[1]
set_location_assignment PIN_173 -to sled[2]
set_location_assignment PIN_175 -to sled[3]
set_location_assignment PIN_207 -to beep
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"