sclock.map.rpt

FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.

; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                       ;
+------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst2|lpm_divide:Mod0 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name         ; Value          ; Type                                 ;
+------------------------+----------------+--------------------------------------+
; LPM_WIDTHN             ; 6              ; Untyped                              ;
; LPM_WIDTHD             ; 4              ; Untyped                              ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                              ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                              ;
; LPM_PIPELINE           ; 0              ; Untyped                              ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                              ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                              ;
; CBXI_PARAMETER         ; lpm_divide_25m ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                              ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                              ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                       ;
+------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: counter:inst2|lpm_divide:Div1 ;
+------------------------+----------------+--------------------------------------+
; Parameter Name         ; Value          ; Type                                 ;
+------------------------+----------------+--------------------------------------+
; LPM_WIDTHN             ; 6              ; Untyped                              ;
; LPM_WIDTHD             ; 4              ; Untyped                              ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                              ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                              ;
; LPM_PIPELINE           ; 0              ; Untyped                              ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                              ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                              ;
; CBXI_PARAMETER         ; lpm_divide_vcm ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                              ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                              ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                       ;
+------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jun 10 16:28:18 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sclock -c sclock
Info: Found 1 design units, including 1 entities, in source file sclock.bdf
    Info: Found entity 1: sclock
Info: Found 1 design units, including 1 entities, in source file segmain.v
    Info: Found entity 1: segmain
Info: Found 1 design units, including 1 entities, in source file div.v
    Info: Found entity 1: div
Info: Found 1 design units, including 1 entities, in source file counter.v
    Info: Found entity 1: counter
Info: Elaborating entity "sclock" for the top level hierarchy
Info: Elaborating entity "counter" for hierarchy "counter:inst2"
Warning (10230): Verilog HDL assignment warning at counter.v(13): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(14): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(15): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(16): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(17): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at counter.v(28): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at counter.v(32): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at counter.v(38): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "div" for hierarchy "div:inst"
Info: Elaborating entity "segmain" for hierarchy "segmain:inst1"
Info: Inferred 4 megafunctions from design logic
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Div0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Mod1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Mod0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Div1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../programfile/altera/q72/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "counter:inst2|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf
    Info: Found entity 1: lpm_divide_vcm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf
    Info: Found entity 1: sign_div_unsign_9kh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf
    Info: Found entity 1: alt_u_div_kve
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "counter:inst2|lpm_divide:Mod1"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf
    Info: Found entity 1: lpm_divide_25m
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "seg_data[7]" stuck at VCC
Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below.
    Info: Register "segmain:inst1|count[15]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[16]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[17]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[18]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[19]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[20]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[21]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[22]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[23]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[24]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[25]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[26]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[27]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[28]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[29]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[30]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[31]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[32]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[33]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[34]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[35]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[36]" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.map.smsg
Info: Implemented 238 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 17 output pins
    Info: Implemented 219 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Allocated 144 megabytes of memory during processing
    Info: Processing ended: Tue Jun 10 16:28:25 2008
    Info: Elapsed time: 00:00:07


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/project/qii/yg2c58eb/ep2c5_project/sclock/sclock.map.smsg.