counter.v

来自「FPGA EP2C5Q288C8 串口原码,测试OK 打开即用.」· Verilog 代码 · 共 51 行

module counter(clk,rst_n,beep,sled,dataout);
input clk;
input rst_n;

output wire beep;
output wire[3:0]sled;
output wire[15:0]dataout;
reg[5:0]scount;
reg[5:0]mcount;
reg[3:0]hcount;

assign sled[3:0]={clk,clk,clk,clk};
assign dataout[3:0]=scount%'d10,
	   dataout[7:4]=scount/'d10,
	   dataout[11:8]=mcount%'d10,
	   dataout[15:12]=mcount/'d10;
assign beep=scount==0?0:1;

always @(negedge rst_n or posedge clk)
begin
	if(!rst_n)
		begin
			scount<=0;
			mcount<=0;
			hcount<=0;
		end
	else if(scount<'d60)
		scount<=scount+'d1;
	else if(mcount<'d60)
			begin
				scount<=0;
				mcount<=mcount+'d1;
			end
	else if(hcount<'d24)
	        begin
			    scount<=0;
				mcount<=0;
				hcount<=hcount+'d1;
			end
	else
		begin
			scount<=0;
			mcount<=0;
			hcount<=0;
		end
end

endmodule