sclock.tan.summary

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.134 ns
From           : rst
To             : lcd:inst3|clkcnt[7]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 28.255 ns
From           : counter:inst2|scount[3]
To             : seg_data[2]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 7.921 ns
From           : rst
To             : lcd:inst3|data[2]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 115.29 MHz ( period = 8.674 ns )
From           : lcd:inst3|counter[1]
To             : lcd:inst3|address[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lcd:inst3|lcd_rw
To             : lcd:inst3|lcd_rw
From Clock     : clk
To Clock       : clk
Failed Paths   : 149

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 149

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