sclock.hif

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sclock
# storage
db|sclock.(0).cnf
db|sclock.(0).cnf
# case_insensitive
# source_file
sclock.bdf
4ae1b8b23a5e1703f7f17ea251c7db9
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
counter
# storage
db|sclock.(1).cnf
db|sclock.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
counter.v
57485e991c83d99de2fe757517f9ee96
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
counter:inst2
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
div
# storage
db|sclock.(2).cnf
db|sclock.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
div.v
b7b591e3cc2923cc1d596c6b83e3ec4e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
CLK_FREQ
00000010111110101111000010000000
PARAMETER_UNSIGNED_BIN
USR
DCLK_FREQ
00000000000000000000000000000010
PARAMETER_UNSIGNED_BIN
USR
}
# hierarchies {
div:inst
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lcd
# storage
db|sclock.(3).cnf
db|sclock.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd.v
35f364c4845297dfe585e07913f7b233
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IDLE
00000000000
PARAMETER_UNSIGNED_BIN
USR
CLEAR
00000000001
PARAMETER_UNSIGNED_BIN
USR
RETURNCURSOR
00000000010
PARAMETER_UNSIGNED_BIN
USR
SETMODE
00000000100
PARAMETER_UNSIGNED_BIN
USR
SWITCHMODE
00000001000
PARAMETER_UNSIGNED_BIN
USR
SHIFT
00000010000
PARAMETER_UNSIGNED_BIN
USR
SETFUNCTION
00000100000
PARAMETER_UNSIGNED_BIN
USR
SETCGRAM
00001000000
PARAMETER_UNSIGNED_BIN
USR
SETDDRAM1
00010000000
PARAMETER_UNSIGNED_BIN
USR
SETDDRAM2
00011000000
PARAMETER_UNSIGNED_BIN
USR
READFLAG
00100000000
PARAMETER_UNSIGNED_BIN
USR
WRITERAM
01000000000
PARAMETER_UNSIGNED_BIN
USR
READRAM
10000000000
PARAMETER_UNSIGNED_BIN
USR
cur_inc
1
PARAMETER_UNKNOWN
USR
cur_dec
0
PARAMETER_UNKNOWN
USR
cur_shift
1
PARAMETER_UNKNOWN
USR
cur_noshift
0
PARAMETER_UNKNOWN
USR
open_display
1
PARAMETER_UNKNOWN
USR
open_cur
0
PARAMETER_UNKNOWN
USR
blank_cur
0
PARAMETER_UNKNOWN
USR
shift_display
1
PARAMETER_UNKNOWN
USR
shift_cur
0
PARAMETER_UNKNOWN
USR
right_shift
1
PARAMETER_UNKNOWN
USR
left_shift
0
PARAMETER_UNKNOWN
USR
datawidth8
1
PARAMETER_UNKNOWN
USR
datawidth4
0
PARAMETER_UNKNOWN
USR
twoline
1
PARAMETER_UNKNOWN
USR
oneline
0
PARAMETER_UNKNOWN
USR
font5x10
1
PARAMETER_UNKNOWN
USR
font5x7
0
PARAMETER_UNKNOWN
USR
}
# hierarchies {
lcd:inst3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
char_ram
# storage
db|sclock.(4).cnf
db|sclock.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
char_ram.vhd
38711ce406a9640fa7e147633d698e1
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
lcd:inst3|char_ram:charram
}
# lmf
e:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
serial_test
# storage
db|sclock.(5).cnf
db|sclock.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
serial_test.vhd
b610c79a5987aca412c8eebb42114fc
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
serial_test:inst4
}
# lmf
e:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
segmain
# storage
db|sclock.(6).cnf
db|sclock.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
segmain.v
63541d9740bf3eddadae4e829eb7242
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
segmain:inst1
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide
# storage
db|sclock.(7).cnf
db|sclock.(7).cnf
# case_insensitive
# source_file
e:|altera|72|quartus|libraries|megafunctions|lpm_divide.tdf
82c565128aa140eaa837be37bb4a9f
6
# user_parameter {
LPM_WIDTHN
6
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_vcm
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# include_file {
e:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
e:|altera|72|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
e:|altera|72|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_vcm
# storage
db|sclock.(8).cnf
db|sclock.(8).cnf
# case_insensitive
# source_file
db|lpm_divide_vcm.tdf
9be33783bf667e71d9b96455abd8e2f
6
# used_port {
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sign_div_unsign_9kh
# storage
db|sclock.(9).cnf
db|sclock.(9).cnf
# case_insensitive
# source_file
db|sign_div_unsign_9kh.tdf
40a2b3149257046b3723f1aebf3ad3e
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
alt_u_div_kve
# storage
db|sclock.(10).cnf
db|sclock.(10).cnf
# case_insensitive
# source_file
db|alt_u_div_kve.tdf
9f9ab33270cf5a4bda55fe2d751614
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_lkc
# storage
db|sclock.(11).cnf
db|sclock.(11).cnf
# case_insensitive
# source_file
db|add_sub_lkc.tdf
ce828b21944d4e3b1dbd859ba8bffb5
6
# used_port {
result0
-1
3
datab0
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_mkc
# storage
db|sclock.(12).cnf
db|sclock.(12).cnf
# case_insensitive
# source_file
db|add_sub_mkc.tdf
3f97cb139d6aad3088ed3c3eafc3fac8
6
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide
# storage
db|sclock.(13).cnf
db|sclock.(13).cnf
# case_insensitive
# source_file
e:|altera|72|quartus|libraries|megafunctions|lpm_divide.tdf
82c565128aa140eaa837be37bb4a9f
6
# user_parameter {
LPM_WIDTHN
6
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_25m
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# include_file {
e:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
e:|altera|72|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
e:|altera|72|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_25m
# storage
db|sclock.(14).cnf
db|sclock.(14).cnf
# case_insensitive
# source_file
db|lpm_divide_25m.tdf
716364f36e329f265e1a33b27f36e58
6
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# lmf
e:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete