sclock.hier_info

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

|sclock
beep <= counter:inst2.beep
rst => div:inst.rst_n
rst => counter:inst2.rst_n
rst => lcd:inst3.rst
rst => segmain:inst1.reset_n
clk => div:inst.clk_in
clk => lcd:inst3.clk
clk => serial_test:inst4.clk
clk => segmain:inst1.clk
lcd_e <= lcd:inst3.lcd_e
lcd_rs <= lcd:inst3.lcd_rs
lcd_rw <= lcd:inst3.lcd_rw
txd <= serial_test:inst4.txd
rxd => serial_test:inst4.rxd
lcd_data[0] <= lcd:inst3.data[0]
lcd_data[1] <= lcd:inst3.data[1]
lcd_data[2] <= lcd:inst3.data[2]
lcd_data[3] <= lcd:inst3.data[3]
lcd_data[4] <= lcd:inst3.data[4]
lcd_data[5] <= lcd:inst3.data[5]
lcd_data[6] <= lcd:inst3.data[6]
lcd_data[7] <= lcd:inst3.data[7]
seg_com[0] <= segmain:inst1.seg_com[0]
seg_com[1] <= segmain:inst1.seg_com[1]
seg_com[2] <= segmain:inst1.seg_com[2]
seg_com[3] <= segmain:inst1.seg_com[3]
seg_data[0] <= segmain:inst1.seg_data[0]
seg_data[1] <= segmain:inst1.seg_data[1]
seg_data[2] <= segmain:inst1.seg_data[2]
seg_data[3] <= segmain:inst1.seg_data[3]
seg_data[4] <= segmain:inst1.seg_data[4]
seg_data[5] <= segmain:inst1.seg_data[5]
seg_data[6] <= segmain:inst1.seg_data[6]
seg_data[7] <= segmain:inst1.seg_data[7]
sled[0] <= counter:inst2.sled[0]
sled[1] <= counter:inst2.sled[1]
sled[2] <= counter:inst2.sled[2]
sled[3] <= counter:inst2.sled[3]


|sclock|counter:inst2
clk => scount[5].CLK
clk => scount[4].CLK
clk => scount[3].CLK
clk => scount[2].CLK
clk => scount[1].CLK
clk => scount[0].CLK
clk => mcount[5].CLK
clk => mcount[4].CLK
clk => mcount[3].CLK
clk => mcount[2].CLK
clk => mcount[1].CLK
clk => mcount[0].CLK
clk => sled[3].DATAIN
clk => sled[2].DATAIN
clk => sled[1].DATAIN
clk => sled[0].DATAIN
rst_n => scount[5].ACLR
rst_n => scount[4].ACLR
rst_n => scount[3].ACLR
rst_n => scount[2].ACLR
rst_n => scount[1].ACLR
rst_n => scount[0].ACLR
rst_n => mcount[5].ACLR
rst_n => mcount[4].ACLR
rst_n => mcount[3].ACLR
rst_n => mcount[2].ACLR
rst_n => mcount[1].ACLR
rst_n => mcount[0].ACLR
beep <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
sled[0] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[1] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[2] <= clk.DB_MAX_OUTPUT_PORT_TYPE
sled[3] <= clk.DB_MAX_OUTPUT_PORT_TYPE
dataout[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
dataout[8] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[9] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[10] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[11] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
dataout[12] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[13] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[14] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
dataout[15] <= Div1.DB_MAX_OUTPUT_PORT_TYPE


|sclock|div:inst
rst_n => clk_div[31].ACLR
rst_n => clk_div[30].ACLR
rst_n => clk_div[29].ACLR
rst_n => clk_div[28].ACLR
rst_n => clk_div[27].ACLR
rst_n => clk_div[26].ACLR
rst_n => clk_div[25].ACLR
rst_n => clk_div[24].ACLR
rst_n => clk_div[23].ACLR
rst_n => clk_div[22].ACLR
rst_n => clk_div[21].ACLR
rst_n => clk_div[20].ACLR
rst_n => clk_div[19].ACLR
rst_n => clk_div[18].ACLR
rst_n => clk_div[17].ACLR
rst_n => clk_div[16].ACLR
rst_n => clk_div[15].ACLR
rst_n => clk_div[14].ACLR
rst_n => clk_div[13].ACLR
rst_n => clk_div[12].ACLR
rst_n => clk_div[11].ACLR
rst_n => clk_div[10].ACLR
rst_n => clk_div[9].ACLR
rst_n => clk_div[8].ACLR
rst_n => clk_div[7].ACLR
rst_n => clk_div[6].ACLR
rst_n => clk_div[5].ACLR
rst_n => clk_div[4].ACLR
rst_n => clk_div[3].ACLR
rst_n => clk_div[2].ACLR
rst_n => clk_div[1].ACLR
rst_n => clk_div[0].ACLR
rst_n => clk_out~reg0.ENA
clk_in => clk_div[31].CLK
clk_in => clk_div[30].CLK
clk_in => clk_div[29].CLK
clk_in => clk_div[28].CLK
clk_in => clk_div[27].CLK
clk_in => clk_div[26].CLK
clk_in => clk_div[25].CLK
clk_in => clk_div[24].CLK
clk_in => clk_div[23].CLK
clk_in => clk_div[22].CLK
clk_in => clk_div[21].CLK
clk_in => clk_div[20].CLK
clk_in => clk_div[19].CLK
clk_in => clk_div[18].CLK
clk_in => clk_div[17].CLK
clk_in => clk_div[16].CLK
clk_in => clk_div[15].CLK
clk_in => clk_div[14].CLK
clk_in => clk_div[13].CLK
clk_in => clk_div[12].CLK
clk_in => clk_div[11].CLK
clk_in => clk_div[10].CLK
clk_in => clk_div[9].CLK
clk_in => clk_div[8].CLK
clk_in => clk_div[7].CLK
clk_in => clk_div[6].CLK
clk_in => clk_div[5].CLK
clk_in => clk_div[4].CLK
clk_in => clk_div[3].CLK
clk_in => clk_div[2].CLK
clk_in => clk_div[1].CLK
clk_in => clk_div[0].CLK
clk_in => clk_out~reg0.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sclock|lcd:inst3
clk => clkcnt[20].CLK
clk => clkcnt[19].CLK
clk => clkcnt[18].CLK
clk => clkcnt[17].CLK
clk => clkcnt[16].CLK
clk => clkcnt[15].CLK
clk => clkcnt[14].CLK
clk => clkcnt[13].CLK
clk => clkcnt[12].CLK
clk => clkcnt[11].CLK
clk => clkcnt[10].CLK
clk => clkcnt[9].CLK
clk => clkcnt[8].CLK
clk => clkcnt[7].CLK
clk => clkcnt[6].CLK
clk => clkcnt[5].CLK
clk => clkcnt[4].CLK
clk => clkcnt[3].CLK
clk => clkcnt[2].CLK
clk => clkcnt[1].CLK
clk => clkcnt[0].CLK
rst => lcd_e~0.OUTPUTSELECT
rst => clk_int~0.OUTPUTSELECT
rst => clkdiv~0.OUTPUTSELECT
rst => clkcnt~21.OUTPUTSELECT
rst => clkcnt~22.OUTPUTSELECT
rst => clkcnt~23.OUTPUTSELECT
rst => clkcnt~24.OUTPUTSELECT
rst => clkcnt~25.OUTPUTSELECT
rst => clkcnt~26.OUTPUTSELECT
rst => clkcnt~27.OUTPUTSELECT
rst => clkcnt~28.OUTPUTSELECT
rst => clkcnt~29.OUTPUTSELECT
rst => clkcnt~30.OUTPUTSELECT
rst => clkcnt~31.OUTPUTSELECT
rst => clkcnt~32.OUTPUTSELECT
rst => clkcnt~33.OUTPUTSELECT
rst => clkcnt~34.OUTPUTSELECT
rst => clkcnt~35.OUTPUTSELECT
rst => clkcnt~36.OUTPUTSELECT
rst => clkcnt~37.OUTPUTSELECT
rst => clkcnt~38.OUTPUTSELECT
rst => clkcnt~39.OUTPUTSELECT
rst => clkcnt~40.OUTPUTSELECT
rst => clkcnt~41.OUTPUTSELECT
rst => counter[6].ACLR
rst => counter[5].ACLR
rst => counter[4].ACLR
rst => counter[3].ACLR
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => address[5].ACLR
rst => address[4].ACLR
rst => address[3].ACLR
rst => address[2].ACLR
rst => address[1].ACLR
rst => address[0].ACLR
rst => flag.ACLR
rst => divcounter[3].ACLR
rst => divcounter[2].ACLR
rst => divcounter[1].ACLR
rst => divcounter[0].ACLR
rst => data[0]~reg0.ENA
rst => lcd_rw~reg0.ENA
rst => lcd_rs~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
rst => state~12.IN1
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sclock|lcd:inst3|char_ram:charram
address[0] => Mux6.IN69
address[0] => Mux5.IN69
address[0] => Mux4.IN69
address[0] => Mux3.IN69
address[0] => Mux2.IN69
address[0] => Mux1.IN69
address[0] => Mux0.IN69
address[1] => Mux6.IN68
address[1] => Mux5.IN68
address[1] => Mux4.IN68
address[1] => Mux3.IN68
address[1] => Mux2.IN68
address[1] => Mux1.IN68
address[1] => Mux0.IN68
address[2] => Mux6.IN67
address[2] => Mux5.IN67
address[2] => Mux4.IN67
address[2] => Mux3.IN67
address[2] => Mux2.IN67
address[2] => Mux1.IN67
address[2] => Mux0.IN67
address[3] => Mux6.IN66
address[3] => Mux5.IN66
address[3] => Mux4.IN66
address[3] => Mux3.IN66
address[3] => Mux2.IN66
address[3] => Mux1.IN66
address[3] => Mux0.IN66
address[4] => Mux6.IN65
address[4] => Mux5.IN65
address[4] => Mux4.IN65
address[4] => Mux3.IN65
address[4] => Mux2.IN65
address[4] => Mux1.IN65
address[4] => Mux0.IN65
address[5] => Mux6.IN64
address[5] => Mux5.IN64
address[5] => Mux4.IN64
address[5] => Mux3.IN64
address[5] => Mux2.IN64
address[5] => Mux1.IN64
address[5] => Mux0.IN64
data[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= <GND>


|sclock|serial_test:inst4
clk => div_reg[15].CLK
clk => div_reg[14].CLK
clk => div_reg[13].CLK
clk => div_reg[12].CLK
clk => div_reg[11].CLK
clk => div_reg[10].CLK
clk => div_reg[9].CLK
clk => div_reg[8].CLK
clk => div_reg[7].CLK
clk => div_reg[6].CLK
clk => div_reg[5].CLK
clk => div_reg[4].CLK
clk => div_reg[3].CLK
clk => div_reg[2].CLK
clk => div_reg[1].CLK
clk => div_reg[0].CLK
clk => clkbaud8x.CLK
rst => div8_tras_reg[0].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[2].ACLR
rst => div8_rec_reg[0].ACLR
rst => div8_rec_reg[1].ACLR
rst => div8_rec_reg[2].ACLR
rst => clkbaud8x.ACLR
rst => div_reg[0].ACLR
rst => div_reg[1].ACLR
rst => div_reg[2].ACLR
rst => div_reg[3].ACLR
rst => div_reg[4].ACLR
rst => div_reg[5].ACLR
rst => div_reg[6].ACLR
rst => div_reg[7].ACLR
rst => div_reg[8].ACLR
rst => div_reg[9].ACLR
rst => div_reg[10].ACLR
rst => div_reg[11].ACLR
rst => div_reg[12].ACLR
rst => div_reg[13].ACLR
rst => div_reg[14].ACLR
rst => div_reg[15].ACLR
rst => recstart_tmp.ACLR
rst => recstart.ACLR
rst => state_rec[0].ACLR
rst => state_rec[1].ACLR
rst => state_rec[2].ACLR
rst => state_rec[3].ACLR
rst => rxd_buf[0].ACLR
rst => rxd_buf[1].ACLR
rst => rxd_buf[2].ACLR
rst => rxd_buf[3].ACLR
rst => rxd_buf[4].ACLR
rst => rxd_buf[5].ACLR
rst => rxd_buf[6].ACLR
rst => rxd_buf[7].ACLR
rst => rxd_reg2.ACLR
rst => rxd_reg1.ACLR
rst => txd_reg.PRESET
rst => trasstart.ACLR
rst => txd_buf[7].ACLR
rst => txd_buf[6].PRESET
rst => txd_buf[5].PRESET
rst => txd_buf[4].PRESET
rst => txd_buf[3].ACLR
rst => txd_buf[2].PRESET
rst => txd_buf[1].PRESET
rst => txd_buf[0].PRESET
rst => state_tras[3].ACLR
rst => state_tras[2].ACLR
rst => state_tras[1].ACLR
rst => state_tras[0].ACLR
rst => send_state[2].ACLR
rst => send_state[1].ACLR
rst => send_state[0].ACLR
rxd => rxd_reg1.DATAIN
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
led[0] <= rxd_buf[0].DB_MAX_OUTPUT_PORT_TYPE
led[1] <= rxd_buf[1].DB_MAX_OUTPUT_PORT_TYPE
led[2] <= rxd_buf[2].DB_MAX_OUTPUT_PORT_TYPE
led[3] <= rxd_buf[3].DB_MAX_OUTPUT_PORT_TYPE
led[4] <= rxd_buf[4].DB_MAX_OUTPUT_PORT_TYPE
led[5] <= rxd_buf[5].DB_MAX_OUTPUT_PORT_TYPE
led[6] <= rxd_buf[6].DB_MAX_OUTPUT_PORT_TYPE
led[7] <= rxd_buf[7].DB_MAX_OUTPUT_PORT_TYPE


|sclock|segmain:inst1
clk => count[36].CLK
clk => count[35].CLK
clk => count[34].CLK
clk => count[33].CLK
clk => count[32].CLK
clk => count[31].CLK
clk => count[30].CLK
clk => count[29].CLK
clk => count[28].CLK
clk => count[27].CLK
clk => count[26].CLK
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
reset_n => count~36.OUTPUTSELECT
reset_n => count~35.OUTPUTSELECT
reset_n => count~34.OUTPUTSELECT
reset_n => count~33.OUTPUTSELECT
reset_n => count~32.OUTPUTSELECT
reset_n => count~31.OUTPUTSELECT
reset_n => count~30.OUTPUTSELECT
reset_n => count~29.OUTPUTSELECT
reset_n => count~28.OUTPUTSELECT
reset_n => count~27.OUTPUTSELECT
reset_n => count~26.OUTPUTSELECT
reset_n => count~25.OUTPUTSELECT
reset_n => count~24.OUTPUTSELECT
reset_n => count~23.OUTPUTSELECT
reset_n => count~22.OUTPUTSELECT
reset_n => count~21.OUTPUTSELECT
reset_n => count~20.OUTPUTSELECT
reset_n => count~19.OUTPUTSELECT
reset_n => count~18.OUTPUTSELECT
reset_n => count~17.OUTPUTSELECT
reset_n => count~16.OUTPUTSELECT
reset_n => count~15.OUTPUTSELECT
reset_n => count~14.OUTPUTSELECT
reset_n => count~13.OUTPUTSELECT
reset_n => count~12.OUTPUTSELECT
reset_n => count~11.OUTPUTSELECT
reset_n => count~10.OUTPUTSELECT
reset_n => count~9.OUTPUTSELECT
reset_n => count~8.OUTPUTSELECT
reset_n => count~7.OUTPUTSELECT
reset_n => count~6.OUTPUTSELECT
reset_n => count~5.OUTPUTSELECT
reset_n => count~4.OUTPUTSELECT
reset_n => count~3.OUTPUTSELECT
reset_n => count~2.OUTPUTSELECT
reset_n => count~1.OUTPUTSELECT
reset_n => count~0.OUTPUTSELECT
datain[0] => Mux3.IN3
datain[1] => Mux2.IN3
datain[2] => Mux1.IN3
datain[3] => Mux0.IN3
datain[4] => Mux3.IN2
datain[5] => Mux2.IN2
datain[6] => Mux1.IN2
datain[7] => Mux0.IN2
datain[8] => Mux3.IN1
datain[9] => Mux2.IN1
datain[10] => Mux1.IN1
datain[11] => Mux0.IN1
datain[12] => Mux3.IN0
datain[13] => Mux2.IN0
datain[14] => Mux1.IN0
datain[15] => Mux0.IN0
seg_data[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
seg_data[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= <VCC>
seg_com[0] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
seg_com[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE