prev_cmp_sclock.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst2\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"counter:inst2\|lpm_divide:Div0\"" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 14 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_vcm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_vcm " "Info: Found entity 1: lpm_divide_vcm" {  } { { "db/lpm_divide_vcm.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/lpm_divide_vcm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Info: Found entity 1: sign_div_unsign_9kh" {  } { { "db/sign_div_unsign_9kh.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/sign_div_unsign_9kh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_kve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_kve " "Info: Found entity 1: alt_u_div_kve" {  } { { "db/alt_u_div_kve.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/alt_u_div_kve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst2\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"counter:inst2\|lpm_divide:Mod1\"" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 15 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_25m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_25m " "Info: Found entity 1: lpm_divide_25m" {  } { { "db/lpm_divide_25m.tdf" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/db/lpm_divide_25m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } } { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[7\] VCC " "Warning (13410): Pin \"seg_data\[7\]\" stuck at VCC" {  } { { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { 224 720 896 240 "seg_data\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "29 29 " "Info: 29 registers lost all their fanouts during netlist optimizations. The first 29 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state.RETURNCURSOR " "Info: Register \"lcd:inst3\|state.RETURNCURSOR\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state.SETCGRAM " "Info: Register \"lcd:inst3\|state.SETCGRAM\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state.SETDDRAM2 " "Info: Register \"lcd:inst3\|state.SETDDRAM2\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state~61 " "Info: Register \"lcd:inst3\|state~61\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state~62 " "Info: Register \"lcd:inst3\|state~62\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state~63 " "Info: Register \"lcd:inst3\|state~63\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lcd:inst3\|state~65 " "Info: Register \"lcd:inst3\|state~65\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[15\] " "Info: Register \"segmain:inst1\|count\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[16\] " "Info: Register \"segmain:inst1\|count\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[17\] " "Info: Register \"segmain:inst1\|count\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[18\] " "Info: Register \"segmain:inst1\|count\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[19\] " "Info: Register \"segmain:inst1\|count\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[20\] " "Info: Register \"segmain:inst1\|count\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[21\] " "Info: Register \"segmain:inst1\|count\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[22\] " "Info: Register \"segmain:inst1\|count\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[23\] " "Info: Register \"segmain:inst1\|count\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[24\] " "Info: Register \"segmain:inst1\|count\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[25\] " "Info: Register \"segmain:inst1\|count\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[26\] " "Info: Register \"segmain:inst1\|count\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[27\] " "Info: Register \"segmain:inst1\|count\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[28\] " "Info: Register \"segmain:inst1\|count\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[29\] " "Info: Register \"segmain:inst1\|count\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[30\] " "Info: Register \"segmain:inst1\|count\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[31\] " "Info: Register \"segmain:inst1\|count\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[32\] " "Info: Register \"segmain:inst1\|count\[32\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[33\] " "Info: Register \"segmain:inst1\|count\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[34\] " "Info: Register \"segmain:inst1\|count\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[35\] " "Info: Register \"segmain:inst1\|count\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst1\|count\[36\] " "Info: Register \"segmain:inst1\|count\[36\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.map.smsg " "Info: Generated suppressed messages file F:/FPGA/ep2c5_project/dl2c58_c5/sclock.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rxd " "Warning (15610): No output dependent on input pin \"rxd\"" {  } { { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { 8 80 248 24 "rxd" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "458 " "Info: Implemented 458 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Info: Implemented 29 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "426 " "Info: Implemented 426 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 34 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 03 23:18:07 2008 " "Info: Processing ended: Wed Dec 03 23:18:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 03 23:18:09 2008 " "Info: Processing started: Wed Dec 03 23:18:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}