prev_cmp_sclock.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(176) " "Warning (10230): Verilog HDL assignment warning at lcd.v(176): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd.v(207) " "Warning (10230): Verilog HDL assignment warning at lcd.v(207): truncated value with size 32 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(208) " "Warning (10230): Verilog HDL assignment warning at lcd.v(208): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(214) " "Warning (10230): Verilog HDL assignment warning at lcd.v(214): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd.v(218) " "Warning (10230): Verilog HDL assignment warning at lcd.v(218): truncated value with size 32 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 218 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(219) " "Warning (10230): Verilog HDL assignment warning at lcd.v(219): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 219 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 lcd.v(224) " "Warning (10230): Verilog HDL assignment warning at lcd.v(224): truncated value with size 7 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 224 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(225) " "Warning (10230): Verilog HDL assignment warning at lcd.v(225): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram lcd:inst3\|char_ram:charram " "Info: Elaborating entity \"char_ram\" for hierarchy \"lcd:inst3\|char_ram:charram\"" {  } { { "lcd.v" "charram" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 237 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serial_test serial_test:inst4 " "Info: Elaborating entity \"serial_test\" for hierarchy \"serial_test:inst4\"" {  } { { "sclock.bdf" "inst4" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -48 312 424 48 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "key_entry2 serial_test.vhd(50) " "Warning (10036): Verilog HDL or VHDL warning at serial_test.vhd(50): object \"key_entry2\" assigned a value but never read" {  } { { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 50 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst1 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst1\"" {  } { { "sclock.bdf" "inst1" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { 200 520 704 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|sclock\|lcd:inst3\|state 11 " "Info: State machine \"\|sclock\|lcd:inst3\|state\" contains 11 states" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|sclock\|lcd:inst3\|state " "Info: Selected Auto state machine encoding method for state machine \"\|sclock\|lcd:inst3\|state\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|sclock\|lcd:inst3\|state " "Info: Encoding result for state machine \"\|sclock\|lcd:inst3\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SETDDRAM2 " "Info: Encoded state bit \"lcd:inst3\|state.SETDDRAM2\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SETDDRAM1 " "Info: Encoded state bit \"lcd:inst3\|state.SETDDRAM1\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SETCGRAM " "Info: Encoded state bit \"lcd:inst3\|state.SETCGRAM\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.IDLE " "Info: Encoded state bit \"lcd:inst3\|state.IDLE\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.WRITERAM " "Info: Encoded state bit \"lcd:inst3\|state.WRITERAM\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SETFUNCTION " "Info: Encoded state bit \"lcd:inst3\|state.SETFUNCTION\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SHIFT " "Info: Encoded state bit \"lcd:inst3\|state.SHIFT\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SWITCHMODE " "Info: Encoded state bit \"lcd:inst3\|state.SWITCHMODE\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.SETMODE " "Info: Encoded state bit \"lcd:inst3\|state.SETMODE\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.RETURNCURSOR " "Info: Encoded state bit \"lcd:inst3\|state.RETURNCURSOR\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "lcd:inst3\|state.CLEAR " "Info: Encoded state bit \"lcd:inst3\|state.CLEAR\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.IDLE 00000000000 " "Info: State \"\|sclock\|lcd:inst3\|state.IDLE\" uses code string \"00000000000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.CLEAR 00010000001 " "Info: State \"\|sclock\|lcd:inst3\|state.CLEAR\" uses code string \"00010000001\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.RETURNCURSOR 00010000010 " "Info: State \"\|sclock\|lcd:inst3\|state.RETURNCURSOR\" uses code string \"00010000010\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SETMODE 00010000100 " "Info: State \"\|sclock\|lcd:inst3\|state.SETMODE\" uses code string \"00010000100\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SWITCHMODE 00010001000 " "Info: State \"\|sclock\|lcd:inst3\|state.SWITCHMODE\" uses code string \"00010001000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SHIFT 00010010000 " "Info: State \"\|sclock\|lcd:inst3\|state.SHIFT\" uses code string \"00010010000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SETFUNCTION 00010100000 " "Info: State \"\|sclock\|lcd:inst3\|state.SETFUNCTION\" uses code string \"00010100000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SETCGRAM 00110000000 " "Info: State \"\|sclock\|lcd:inst3\|state.SETCGRAM\" uses code string \"00110000000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SETDDRAM1 01010000000 " "Info: State \"\|sclock\|lcd:inst3\|state.SETDDRAM1\" uses code string \"01010000000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.SETDDRAM2 10010000000 " "Info: State \"\|sclock\|lcd:inst3\|state.SETDDRAM2\" uses code string \"10010000000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sclock\|lcd:inst3\|state.WRITERAM 00011000000 " "Info: State \"\|sclock\|lcd:inst3\|state.WRITERAM\" uses code string \"00011000000\"" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 10 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "serial_test:inst4\|txd_buf\[7\] data_in GND " "Warning (14130): Reduced register \"serial_test:inst4\|txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 144 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Div0\"" {  } { { "counter.v" "Div0" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 14 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Mod1\"" {  } { { "counter.v" "Mod1" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 15 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Mod0\"" {  } { { "counter.v" "Mod0" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 13 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "counter:inst2\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"counter:inst2\|Div1\"" {  } { { "counter.v" "Div1" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 16 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}