prev_cmp_sclock.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 counter.v(17) " "Warning (10230): Verilog HDL assignment warning at counter.v(17): truncated value with size 32 to match size of target (1)" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 counter.v(28) " "Warning (10230): Verilog HDL assignment warning at counter.v(28): truncated value with size 32 to match size of target (6)" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 counter.v(32) " "Warning (10230): Verilog HDL assignment warning at counter.v(32): truncated value with size 32 to match size of target (6)" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(38) " "Warning (10230): Verilog HDL assignment warning at counter.v(38): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/counter.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "sclock.bdf" "inst" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { 200 104 224 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst3 " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst3\"" {  } { { "sclock.bdf" "inst3" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -232 208 320 -104 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd.v(72) " "Warning (10230): Verilog HDL assignment warning at lcd.v(72): truncated value with size 32 to match size of target (21)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(76) " "Warning (10230): Verilog HDL assignment warning at lcd.v(76): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd.v(122) " "Warning (10230): Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (4)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(142) " "Warning (10230): Verilog HDL assignment warning at lcd.v(142): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(143) " "Warning (10230): Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(156) " "Warning (10230): Verilog HDL assignment warning at lcd.v(156): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 156 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(157) " "Warning (10230): Verilog HDL assignment warning at lcd.v(157): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(158) " "Warning (10230): Verilog HDL assignment warning at lcd.v(158): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(165) " "Warning (10230): Verilog HDL assignment warning at lcd.v(165): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(166) " "Warning (10230): Verilog HDL assignment warning at lcd.v(166): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(174) " "Warning (10230): Verilog HDL assignment warning at lcd.v(174): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(175) " "Warning (10230): Verilog HDL assignment warning at lcd.v(175): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 175 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}