sclock.tan.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Info" "ITDB_TSU_RESULT" "lcd:inst3\|clkcnt\[8\] rst clk 7.134 ns register " "Info: tsu for register \"lcd:inst3\|clkcnt\[8\]\" (data pin = \"rst\", clock pin = \"clk\") is 7.134 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.481 ns + Longest pin register " "Info: + Longest pin to register delay is 10.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns rst 1 PIN PIN_206 100 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 100; PIN Node = 'rst'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -64 -240 -72 -48 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.177 ns) + CELL(0.589 ns) 8.770 ns lcd:inst3\|clkcnt\[2\]~240 2 COMB LCCOMB_X15_Y16_N28 21 " "Info: 2: + IC(7.177 ns) + CELL(0.589 ns) = 8.770 ns; Loc. = LCCOMB_X15_Y16_N28; Fanout = 21; COMB Node = 'lcd:inst3\|clkcnt\[2\]~240'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.766 ns" { rst lcd:inst3|clkcnt[2]~240 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.660 ns) 10.481 ns lcd:inst3\|clkcnt\[8\] 3 REG LCFF_X15_Y13_N29 3 " "Info: 3: + IC(1.051 ns) + CELL(0.660 ns) = 10.481 ns; Loc. = LCFF_X15_Y13_N29; Fanout = 3; REG Node = 'lcd:inst3\|clkcnt\[8\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.711 ns" { lcd:inst3|clkcnt[2]~240 lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.253 ns ( 21.50 % ) " "Info: Total cell delay = 2.253 ns ( 21.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.228 ns ( 78.50 % ) " "Info: Total interconnect delay = 8.228 ns ( 78.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.481 ns" { rst lcd:inst3|clkcnt[2]~240 lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.481 ns" { rst {} rst~combout {} lcd:inst3|clkcnt[2]~240 {} lcd:inst3|clkcnt[8] {} } { 0.000ns 0.000ns 7.177ns 1.051ns } { 0.000ns 1.004ns 0.589ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.307 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.307 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.666 ns) 3.307 ns lcd:inst3\|clkcnt\[8\] 2 REG LCFF_X15_Y13_N29 3 " "Info: 2: + IC(1.501 ns) + CELL(0.666 ns) = 3.307 ns; Loc. = LCFF_X15_Y13_N29; Fanout = 3; REG Node = 'lcd:inst3\|clkcnt\[8\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.167 ns" { clk lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 54.61 % ) " "Info: Total cell delay = 1.806 ns ( 54.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.501 ns ( 45.39 % ) " "Info: Total interconnect delay = 1.501 ns ( 45.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.307 ns" { clk lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.307 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[8] {} } { 0.000ns 0.000ns 1.501ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.481 ns" { rst lcd:inst3|clkcnt[2]~240 lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.481 ns" { rst {} rst~combout {} lcd:inst3|clkcnt[2]~240 {} lcd:inst3|clkcnt[8] {} } { 0.000ns 0.000ns 7.177ns 1.051ns } { 0.000ns 1.004ns 0.589ns 0.660ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.307 ns" { clk lcd:inst3|clkcnt[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.307 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[8] {} } { 0.000ns 0.000ns 1.501ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[2\] counter:inst2\|scount\[3\] 28.255 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[2\]\" through register \"counter:inst2\|scount\[3\]\" is 28.255 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.422 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.970 ns) 3.611 ns div:inst\|clk_out 2 REG LCFF_X15_Y13_N11 6 " "Info: 2: + IC(1.501 ns) + CELL(0.970 ns) = 3.611 ns; Loc. = LCFF_X15_Y13_N11; Fanout = 6; REG Node = 'div:inst\|clk_out'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk div:inst|clk_o