sclock.tan.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 149 " "Warning: Circuit may not operate. Detected 149 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst3\|lcd_rw lcd:inst3\|lcd_rw clk 2.595 ns " "Info: Found hold time violation between source  pin or register \"lcd:inst3\|lcd_rw\" and destination pin or register \"lcd:inst3\|lcd_rw\" for clock \"clk\" (Hold time is 2.595 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.094 ns + Largest " "Info: + Largest clock skew is 3.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.228 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 16.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.970 ns) 3.611 ns lcd:inst3\|clkcnt\[11\] 2 REG LCFF_X15_Y12_N3 3 " "Info: 2: + IC(1.501 ns) + CELL(0.970 ns) = 3.611 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 3; REG Node = 'lcd:inst3\|clkcnt\[11\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk lcd:inst3|clkcnt[11] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.156 ns) + CELL(0.534 ns) 5.301 ns lcd:inst3\|Equal0~215 3 COMB LCCOMB_X15_Y13_N8 1 " "Info: 3: + IC(1.156 ns) + CELL(0.534 ns) = 5.301 ns; Loc. = LCCOMB_X15_Y13_N8; Fanout = 1; COMB Node = 'lcd:inst3\|Equal0~215'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.690 ns" { lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.742 ns) + CELL(0.614 ns) 7.657 ns lcd:inst3\|Equal0~217 4 COMB LCCOMB_X15_Y16_N8 1 " "Info: 4: + IC(1.742 ns) + CELL(0.614 ns) = 7.657 ns; Loc. = LCCOMB_X15_Y16_N8; Fanout = 1; COMB Node = 'lcd:inst3\|Equal0~217'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.356 ns" { lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.370 ns) 8.416 ns lcd:inst3\|Equal0 5 COMB LCCOMB_X15_Y16_N2 2 " "Info: 5: + IC(0.389 ns) + CELL(0.370 ns) = 8.416 ns; Loc. = LCCOMB_X15_Y16_N2; Fanout = 2; COMB Node = 'lcd:inst3\|Equal0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.759 ns" { lcd:inst3|Equal0~217 lcd:inst3|Equal0 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.970 ns) 10.419 ns lcd:inst3\|clkdiv 6 REG LCFF_X16_Y15_N1 3 " "Info: 6: + IC(1.033 ns) + CELL(0.970 ns) = 10.419 ns; Loc. = LCFF_X16_Y15_N1; Fanout = 3; REG Node = 'lcd:inst3\|clkdiv'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.003 ns" { lcd:inst3|Equal0 lcd:inst3|clkdiv } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.970 ns) 12.504 ns lcd:inst3\|clk_int 7 REG LCFF_X17_Y13_N5 2 " "Info: 7: + IC(1.115 ns) + CELL(0.970 ns) = 12.504 ns; Loc. = LCFF_X17_Y13_N5; Fanout = 2; REG Node = 'lcd:inst3\|clk_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { lcd:inst3|clkdiv lcd:inst3|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.123 ns) + CELL(0.000 ns) 14.627 ns lcd:inst3\|clk_int~clkctrl 8 COMB CLKCTRL_G1 36 " "Info: 8: + IC(2.123 ns) + CELL(0.000 ns) = 14.627 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'lcd:inst3\|clk_int~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.123 ns" { lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.666 ns) 16.228 ns lcd:inst3\|lcd_rw 9 REG LCFF_X16_Y16_N27 2 " "Info: 9: + IC(0.935 ns) + CELL(0.666 ns) = 16.228 ns; Loc. = LCFF_X16_Y16_N27; Fanout = 2; REG Node = 'lcd:inst3\|lcd_rw'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.234 ns ( 38.42 % ) " "Info: Total cell delay = 6.234 ns ( 38.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.994 ns ( 61.58 % ) " "Info: Total interconnect delay = 9.994 ns ( 61.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.228 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.228 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.134 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 13.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.970 ns) 3.611 ns lcd:inst3\|clkcnt\[20\] 2 REG LCFF_X15_Y12_N21 2 " "Info: 2: + IC(1.501 ns) + CELL(0.970 ns) = 3.611 ns; Loc. = LCFF_X15_Y12_N21; Fanout = 2; REG Node = 'lcd:inst3\|clkcnt\[20\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk lcd:inst3|clkcnt[20] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.499 ns) 5.322 ns lcd:inst3\|Equal0 3 COMB LCCOMB_X15_Y16_N2 2 " "Info: 3: + IC(1.212 ns) + CELL(0.499 ns) = 5.322 ns; Loc. = LCCOMB_X15_Y16_N2; Fanout = 2; COMB Node = 'lcd:inst3\|Equal0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.711 ns" { lcd:inst3|clkcnt[20] lcd:inst3|Equal0 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.970 ns) 7.325 ns lcd:inst3\|clkdiv 4 REG LCFF_X16_Y15_N1 3 " "Info: 4: + IC(1.033 ns) + CELL(0.970 ns) = 7.325 ns; Loc. = LCFF_X16_Y15_N1; Fanout = 3; REG Node = 'lcd:inst3\|clkdiv'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.003 ns" { lcd:inst3|Equal0 lcd:inst3|clkdiv } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.970 ns) 9.410 ns lcd:inst3\|clk_int 5 REG LCFF_X17_Y13_N5 2 " "Info: 5: + IC(1.115 ns) + CELL(0.970 ns) = 9.410 ns; Loc. = LCFF_X17_Y13_N5; Fanout = 2; REG Node = 'lcd:inst3\|clk_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { lcd:inst3|clkdiv lcd:inst3|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.123 ns) + CELL(0.000 ns) 11.533 ns lcd:inst3\|clk_int~clkctrl 6 COMB CLKCTRL_G1 36 " "Info: 6: + IC(2.123 ns) + CELL(0.000 ns) = 11.533 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'lcd:inst3\|clk_int~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.123 ns" { lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.666 ns) 13.134 ns lcd:inst3\|lcd_rw 7 REG LCFF_X16_Y16_N27 2 " "Info: 7: + IC(0.935 ns) + CELL(0.666 ns) = 13.134 ns; Loc. = LCFF_X16_Y16_N27; Fanout = 2; REG Node = 'lcd:inst3\|lcd_rw'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.215 ns ( 39.71 % ) " "Info: Total cell delay = 5.215 ns ( 39.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.919 ns ( 60.29 % ) " "Info: Total interconnect delay = 7.919 ns ( 60.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.134 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.134 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.228 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.228 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.134 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.134 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns - Shortest register register " "Info: - Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst3\|lcd_rw 1 REG LCFF_X16_Y16_N27 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y16_N27; Fanout = 2; REG Node = 'lcd:inst3\|lcd_rw'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst3|lcd_rw } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns lcd:inst3\|lcd_rw~48 2 COMB LCCOMB_X16_Y16_N26 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X16_Y16_N26; Fanout = 1; COMB Node = 'lcd:inst3\|lcd_rw~48'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { lcd:inst3|lcd_rw lcd:inst3|lcd_rw~48 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns lcd:inst3\|lcd_rw 3 REG LCFF_X16_Y16_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X16_Y16_N27; Fanout = 2; REG Node = 'lcd:inst3\|lcd_rw'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { lcd:inst3|lcd_rw~48 lcd:inst3|lcd_rw } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { lcd:inst3|lcd_rw lcd:inst3|lcd_rw~48 lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { lcd:inst3|lcd_rw {} lcd:inst3|lcd_rw~48 {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 3 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.228 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.228 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.134 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.134 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.935ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { lcd:inst3|lcd_rw lcd:inst3|lcd_rw~48 lcd:inst3|lcd_rw } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { lcd:inst3|lcd_rw {} lcd:inst3|lcd_rw~48 {} lcd:inst3|lcd_rw {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}