sclock.tan.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "31 " "Warning: Found 31 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "serial_test:inst4\|clkbaud8x " "Info: Detected ripple clock \"serial_test:inst4\|clkbaud8x\" as buffer" {  } { { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 40 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "serial_test:inst4\|clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[7\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[6\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[5\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[4\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[0\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[2\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[1\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[3\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[15\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[12\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[14\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[13\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[9\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[8\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[10\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[11\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[16\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[16\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[18\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[18\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[17\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[17\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[19\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[19\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0~214 " "Info: Detected gated clock \"lcd:inst3\|Equal0~214\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0~214" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0~213 " "Info: Detected gated clock \"lcd:inst3\|Equal0~213\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0~213" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0~216 " "Info: Detected gated clock \"lcd:inst3\|Equal0~216\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0~216" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0~215 " "Info: Detected gated clock \"lcd:inst3\|Equal0~215\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0~215" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0~218 " "Info: Detected gated clock \"lcd:inst3\|Equal0~218\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0~218" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkcnt\[20\] " "Info: Detected ripple clock \"lcd:inst3\|clkcnt\[20\]\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkcnt\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "lcd:inst3\|Equal0 " "Info: Detected gated clock \"lcd:inst3\|Equal0\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|Equal0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clkdiv " "Info: Detected ripple clock \"lcd:inst3\|clkdiv\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 78 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clkdiv" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst3\|clk_int " "Info: Detected ripple clock \"lcd:inst3\|clk_int\" as buffer" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst3\|clk_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "div:inst\|clk_out " "Info: Detected ripple clock \"div:inst\|clk_out\" as buffer" {  } { { "div.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/div.v" 10 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "div:inst\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst3\|counter\[1\] register lcd:inst3\|address\[0\] 115.29 MHz 8.674 ns Internal " "Info: Clock \"clk\" has Internal fmax of 115.29 MHz between source register \"lcd:inst3\|counter\[1\]\" and destination register \"lcd:inst3\|address\[0\]\" (period= 8.674 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.344 ns + Longest register register " "Info: + Longest register to register delay is 5.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst3\|counter\[1\] 1 REG LCFF_X19_Y16_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y16_N1; Fanout = 9; REG Node = 'lcd:inst3\|counter\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst3|counter[1] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.123 ns) + CELL(0.370 ns) 1.493 ns lcd:inst3\|Equal2~66 2 COMB LCCOMB_X17_Y16_N2 1 " "Info: 2: + IC(1.123 ns) + CELL(0.370 ns) = 1.493 ns; Loc. = LCCOMB_X17_Y16_N2; Fanout = 1; COMB Node = 'lcd:inst3\|Equal2~66'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { lcd:inst3|counter[1] lcd:inst3|Equal2~66 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 2.060 ns lcd:inst3\|Equal2~67 3 COMB LCCOMB_X17_Y16_N14 2 " "Info: 3: + IC(0.361 ns) + CELL(0.206 ns) = 2.060 ns; Loc. = LCCOMB_X17_Y16_N14; Fanout = 2; COMB Node = 'lcd:inst3\|Equal2~67'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { lcd:inst3|Equal2~66 lcd:inst3|Equal2~67 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.613 ns) + CELL(0.206 ns) 2.879 ns lcd:inst3\|Equal2~68 4 COMB LCCOMB_X18_Y16_N0 3 " "Info: 4: + IC(0.613 ns) + CELL(0.206 ns) = 2.879 ns; Loc. = LCCOMB_X18_Y16_N0; Fanout = 3; COMB Node = 'lcd:inst3\|Equal2~68'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.819 ns" { lcd:inst3|Equal2~67 lcd:inst3|Equal2~68 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 3.446 ns lcd:inst3\|address\[5\]~905 5 COMB LCCOMB_X18_Y16_N10 6 " "Info: 5: + IC(0.361 ns) + CELL(0.206 ns) = 3.446 ns; Loc. = LCCOMB_X18_Y16_N10; Fanout = 6; COMB Node = 'lcd:inst3\|address\[5\]~905'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { lcd:inst3|Equal2~68 lcd:inst3|address[5]~905 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.855 ns) 5.344 ns lcd:inst3\|address\[0\] 6 REG LCFF_X15_Y16_N13 12 " "Info: 6: + IC(1.043 ns) + CELL(0.855 ns) = 5.344 ns; Loc. = LCFF_X15_Y16_N13; Fanout = 12; REG Node = 'lcd:inst3\|address\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.898 ns" { lcd:inst3|address[5]~905 lcd:inst3|address[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.843 ns ( 34.49 % ) " "Info: Total cell delay = 1.843 ns ( 34.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.501 ns ( 65.51 % ) " "Info: Total interconnect delay = 3.501 ns ( 65.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.344 ns" { lcd:inst3|counter[1] lcd:inst3|Equal2~66 lcd:inst3|Equal2~67 lcd:inst3|Equal2~68 lcd:inst3|address[5]~905 lcd:inst3|address[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.344 ns" { lcd:inst3|counter[1] {} lcd:inst3|Equal2~66 {} lcd:inst3|Equal2~67 {} lcd:inst3|Equal2~68 {} lcd:inst3|address[5]~905 {} lcd:inst3|address[0] {} } { 0.000ns 1.123ns 0.361ns 0.613ns 0.361ns 1.043ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.066 ns - Smallest " "Info: - Smallest clock skew is -3.066 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.133 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 13.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.970 ns) 3.611 ns lcd:inst3\|clkcnt\[20\] 2 REG LCFF_X15_Y12_N21 2 " "Info: 2: + IC(1.501 ns) + CELL(0.970 ns) = 3.611 ns; Loc. = LCFF_X15_Y12_N21; Fanout = 2; REG Node = 'lcd:inst3\|clkcnt\[20\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk lcd:inst3|clkcnt[20] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.499 ns) 5.322 ns lcd:inst3\|Equal0 3 COMB LCCOMB_X15_Y16_N2 2 " "Info: 3: + IC(1.212 ns) + CELL(0.499 ns) = 5.322 ns; Loc. = LCCOMB_X15_Y16_N2; Fanout = 2; COMB Node = 'lcd:inst3\|Equal0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.711 ns" { lcd:inst3|clkcnt[20] lcd:inst3|Equal0 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.970 ns) 7.325 ns lcd:inst3\|clkdiv 4 REG LCFF_X16_Y15_N1 3 " "Info: 4: + IC(1.033 ns) + CELL(0.970 ns) = 7.325 ns; Loc. = LCFF_X16_Y15_N1; Fanout = 3; REG Node = 'lcd:inst3\|clkdiv'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.003 ns" { lcd:inst3|Equal0 lcd:inst3|clkdiv } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.970 ns) 9.410 ns lcd:inst3\|clk_int 5 REG LCFF_X17_Y13_N5 2 " "Info: 5: + IC(1.115 ns) + CELL(0.970 ns) = 9.410 ns; Loc. = LCFF_X17_Y13_N5; Fanout = 2; REG Node = 'lcd:inst3\|clk_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { lcd:inst3|clkdiv lcd:inst3|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.123 ns) + CELL(0.000 ns) 11.533 ns lcd:inst3\|clk_int~clkctrl 6 COMB CLKCTRL_G1 36 " "Info: 6: + IC(2.123 ns) + CELL(0.000 ns) = 11.533 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'lcd:inst3\|clk_int~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.123 ns" { lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.666 ns) 13.133 ns lcd:inst3\|address\[0\] 7 REG LCFF_X15_Y16_N13 12 " "Info: 7: + IC(0.934 ns) + CELL(0.666 ns) = 13.133 ns; Loc. = LCFF_X15_Y16_N13; Fanout = 12; REG Node = 'lcd:inst3\|address\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lcd:inst3|clk_int~clkctrl lcd:inst3|address[0] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.215 ns ( 39.71 % ) " "Info: Total cell delay = 5.215 ns ( 39.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.918 ns ( 60.29 % ) " "Info: Total interconnect delay = 7.918 ns ( 60.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.133 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|address[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.133 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|address[0] {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.934ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.199 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 16.199 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 24 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 24; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sclock.bdf" "" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -80 -240 -72 -64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.970 ns) 3.611 ns lcd:inst3\|clkcnt\[11\] 2 REG LCFF_X15_Y12_N3 3 " "Info: 2: + IC(1.501 ns) + CELL(0.970 ns) = 3.611 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 3; REG Node = 'lcd:inst3\|clkcnt\[11\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk lcd:inst3|clkcnt[11] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.156 ns) + CELL(0.534 ns) 5.301 ns lcd:inst3\|Equal0~215 3 COMB LCCOMB_X15_Y13_N8 1 " "Info: 3: + IC(1.156 ns) + CELL(0.534 ns) = 5.301 ns; Loc. = LCCOMB_X15_Y13_N8; Fanout = 1; COMB Node = 'lcd:inst3\|Equal0~215'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.690 ns" { lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.742 ns) + CELL(0.614 ns) 7.657 ns lcd:inst3\|Equal0~217 4 COMB LCCOMB_X15_Y16_N8 1 " "Info: 4: + IC(1.742 ns) + CELL(0.614 ns) = 7.657 ns; Loc. = LCCOMB_X15_Y16_N8; Fanout = 1; COMB Node = 'lcd:inst3\|Equal0~217'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.356 ns" { lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.370 ns) 8.416 ns lcd:inst3\|Equal0 5 COMB LCCOMB_X15_Y16_N2 2 " "Info: 5: + IC(0.389 ns) + CELL(0.370 ns) = 8.416 ns; Loc. = LCCOMB_X15_Y16_N2; Fanout = 2; COMB Node = 'lcd:inst3\|Equal0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.759 ns" { lcd:inst3|Equal0~217 lcd:inst3|Equal0 } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.970 ns) 10.419 ns lcd:inst3\|clkdiv 6 REG LCFF_X16_Y15_N1 3 " "Info: 6: + IC(1.033 ns) + CELL(0.970 ns) = 10.419 ns; Loc. = LCFF_X16_Y15_N1; Fanout = 3; REG Node = 'lcd:inst3\|clkdiv'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.003 ns" { lcd:inst3|Equal0 lcd:inst3|clkdiv } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.970 ns) 12.504 ns lcd:inst3\|clk_int 7 REG LCFF_X17_Y13_N5 2 " "Info: 7: + IC(1.115 ns) + CELL(0.970 ns) = 12.504 ns; Loc. = LCFF_X17_Y13_N5; Fanout = 2; REG Node = 'lcd:inst3\|clk_int'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { lcd:inst3|clkdiv lcd:inst3|clk_int } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.123 ns) + CELL(0.000 ns) 14.627 ns lcd:inst3\|clk_int~clkctrl 8 COMB CLKCTRL_G1 36 " "Info: 8: + IC(2.123 ns) + CELL(0.000 ns) = 14.627 ns; Loc. = CLKCTRL_G1; Fanout = 36; COMB Node = 'lcd:inst3\|clk_int~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.123 ns" { lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 16.199 ns lcd:inst3\|counter\[1\] 9 REG LCFF_X19_Y16_N1 9 " "Info: 9: + IC(0.906 ns) + CELL(0.666 ns) = 16.199 ns; Loc. = LCFF_X19_Y16_N1; Fanout = 9; REG Node = 'lcd:inst3\|counter\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { lcd:inst3|clk_int~clkctrl lcd:inst3|counter[1] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.234 ns ( 38.48 % ) " "Info: Total cell delay = 6.234 ns ( 38.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.965 ns ( 61.52 % ) " "Info: Total interconnect delay = 9.965 ns ( 61.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.199 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|counter[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.199 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|counter[1] {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.906ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.133 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|address[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.133 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|address[0] {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.934ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.199 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|counter[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.199 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|counter[1] {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.906ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 235 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.344 ns" { lcd:inst3|counter[1] lcd:inst3|Equal2~66 lcd:inst3|Equal2~67 lcd:inst3|Equal2~68 lcd:inst3|address[5]~905 lcd:inst3|address[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.344 ns" { lcd:inst3|counter[1] {} lcd:inst3|Equal2~66 {} lcd:inst3|Equal2~67 {} lcd:inst3|Equal2~68 {} lcd:inst3|address[5]~905 {} lcd:inst3|address[0] {} } { 0.000ns 1.123ns 0.361ns 0.613ns 0.361ns 1.043ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.206ns 0.855ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.133 ns" { clk lcd:inst3|clkcnt[20] lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|address[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.133 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[20] {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|address[0] {} } { 0.000ns 0.000ns 1.501ns 1.212ns 1.033ns 1.115ns 2.123ns 0.934ns } { 0.000ns 1.140ns 0.970ns 0.499ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.199 ns" { clk lcd:inst3|clkcnt[11] lcd:inst3|Equal0~215 lcd:inst3|Equal0~217 lcd:inst3|Equal0 lcd:inst3|clkdiv lcd:inst3|clk_int lcd:inst3|clk_int~clkctrl lcd:inst3|counter[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.199 ns" { clk {} clk~combout {} lcd:inst3|clkcnt[11] {} lcd:inst3|Equal0~215 {} lcd:inst3|Equal0~217 {} lcd:inst3|Equal0 {} lcd:inst3|clkdiv {} lcd:inst3|clk_int {} lcd:inst3|clk_int~clkctrl {} lcd:inst3|counter[1] {} } { 0.000ns 0.000ns 1.501ns 1.156ns 1.742ns 0.389ns 1.033ns 1.115ns 2.123ns 0.906ns } { 0.000ns 1.140ns 0.970ns 0.534ns 0.614ns 0.370ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}