sclock.map.qmsg

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd.v(72) " "Warning (10230): Verilog HDL assignment warning at lcd.v(72): truncated value with size 32 to match size of target (21)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(76) " "Warning (10230): Verilog HDL assignment warning at lcd.v(76): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd.v(122) " "Warning (10230): Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (4)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(142) " "Warning (10230): Verilog HDL assignment warning at lcd.v(142): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(143) " "Warning (10230): Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(156) " "Warning (10230): Verilog HDL assignment warning at lcd.v(156): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 156 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(157) " "Warning (10230): Verilog HDL assignment warning at lcd.v(157): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(158) " "Warning (10230): Verilog HDL assignment warning at lcd.v(158): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(165) " "Warning (10230): Verilog HDL assignment warning at lcd.v(165): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(166) " "Warning (10230): Verilog HDL assignment warning at lcd.v(166): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(174) " "Warning (10230): Verilog HDL assignment warning at lcd.v(174): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(175) " "Warning (10230): Verilog HDL assignment warning at lcd.v(175): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 175 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(176) " "Warning (10230): Verilog HDL assignment warning at lcd.v(176): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd.v(207) " "Warning (10230): Verilog HDL assignment warning at lcd.v(207): truncated value with size 32 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(208) " "Warning (10230): Verilog HDL assignment warning at lcd.v(208): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(214) " "Warning (10230): Verilog HDL assignment warning at lcd.v(214): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd.v(218) " "Warning (10230): Verilog HDL assignment warning at lcd.v(218): truncated value with size 32 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 218 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(219) " "Warning (10230): Verilog HDL assignment warning at lcd.v(219): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 219 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 lcd.v(224) " "Warning (10230): Verilog HDL assignment warning at lcd.v(224): truncated value with size 7 to match size of target (6)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 224 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(225) " "Warning (10230): Verilog HDL assignment warning at lcd.v(225): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram lcd:inst3\|char_ram:charram " "Info: Elaborating entity \"char_ram\" for hierarchy \"lcd:inst3\|char_ram:charram\"" {  } { { "lcd.v" "charram" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/lcd.v" 237 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serial_test serial_test:inst4 " "Info: Elaborating entity \"serial_test\" for hierarchy \"serial_test:inst4\"" {  } { { "sclock.bdf" "inst4" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { -48 312 424 48 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "key_entry2 serial_test.vhd(50) " "Warning (10036): Verilog HDL or VHDL warning at serial_test.vhd(50): object \"key_entry2\" assigned a value but never read" {  } { { "serial_test.vhd" "" { Text "F:/FPGA/ep2c5_project/dl2c58_c5/serial_test.vhd" 50 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst1 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst1\"" {  } { { "sclock.bdf" "inst1" { Schematic "F:/FPGA/ep2c5_project/dl2c58_c5/sclock.bdf" { { 200 520 704 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}