sclock.map.rpt

FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.

    Info: Found entity 1: sclock
Info: Found 1 design units, including 1 entities, in source file segmain.v
    Info: Found entity 1: segmain
Info: Found 1 design units, including 1 entities, in source file div.v
    Info: Found entity 1: div
Info: Found 1 design units, including 1 entities, in source file counter.v
    Info: Found entity 1: counter
Info: Found 1 design units, including 1 entities, in source file lcd.v
    Info: Found entity 1: lcd
Info: Found 2 design units, including 1 entities, in source file serial_test.vhd
    Info: Found design unit 1: serial_test-arch
    Info: Found entity 1: serial_test
Info: Found 2 design units, including 1 entities, in source file char_ram.vhd
    Info: Found design unit 1: char_ram-fun
    Info: Found entity 1: char_ram
Info: Elaborating entity "sclock" for the top level hierarchy
Info: Elaborating entity "counter" for hierarchy "counter:inst2"
Warning (10230): Verilog HDL assignment warning at counter.v(13): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(14): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(15): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(16): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter.v(17): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at counter.v(28): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at counter.v(32): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at counter.v(38): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "div" for hierarchy "div:inst"
Info: Elaborating entity "lcd" for hierarchy "lcd:inst3"
Warning (10230): Verilog HDL assignment warning at lcd.v(72): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at lcd.v(76): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at lcd.v(142): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(156): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(157): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(158): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(165): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(166): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(174): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(175): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(176): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(207): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at lcd.v(208): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at lcd.v(214): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at lcd.v(218): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at lcd.v(219): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at lcd.v(224): truncated value with size 7 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at lcd.v(225): truncated value with size 32 to match size of target (7)
Info: Elaborating entity "char_ram" for hierarchy "lcd:inst3|char_ram:charram"
Info: Elaborating entity "serial_test" for hierarchy "serial_test:inst4"
Warning (10036): Verilog HDL or VHDL warning at serial_test.vhd(50): object "key_entry2" assigned a value but never read
Info: Elaborating entity "segmain" for hierarchy "segmain:inst1"
Info: State machine "|sclock|lcd:inst3|state" contains 11 states
Info: Selected Auto state machine encoding method for state machine "|sclock|lcd:inst3|state"
Info: Encoding result for state machine "|sclock|lcd:inst3|state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "lcd:inst3|state.SETDDRAM2"
        Info: Encoded state bit "lcd:inst3|state.SETDDRAM1"
        Info: Encoded state bit "lcd:inst3|state.SETCGRAM"
        Info: Encoded state bit "lcd:inst3|state.IDLE"
        Info: Encoded state bit "lcd:inst3|state.WRITERAM"
        Info: Encoded state bit "lcd:inst3|state.SETFUNCTION"
        Info: Encoded state bit "lcd:inst3|state.SHIFT"
        Info: Encoded state bit "lcd:inst3|state.SWITCHMODE"
        Info: Encoded state bit "lcd:inst3|state.SETMODE"
        Info: Encoded state bit "lcd:inst3|state.RETURNCURSOR"
        Info: Encoded state bit "lcd:inst3|state.CLEAR"
    Info: State "|sclock|lcd:inst3|state.IDLE" uses code string "00000000000"
    Info: State "|sclock|lcd:inst3|state.CLEAR" uses code string "00010000001"
    Info: State "|sclock|lcd:inst3|state.RETURNCURSOR" uses code string "00010000010"
    Info: State "|sclock|lcd:inst3|state.SETMODE" uses code string "00010000100"
    Info: State "|sclock|lcd:inst3|state.SWITCHMODE" uses code string "00010001000"
    Info: State "|sclock|lcd:inst3|state.SHIFT" uses code string "00010010000"
    Info: State "|sclock|lcd:inst3|state.SETFUNCTION" uses code string "00010100000"
    Info: State "|sclock|lcd:inst3|state.SETCGRAM" uses code string "00110000000"
    Info: State "|sclock|lcd:inst3|state.SETDDRAM1" uses code string "01010000000"
    Info: State "|sclock|lcd:inst3|state.SETDDRAM2" uses code string "10010000000"
    Info: State "|sclock|lcd:inst3|state.WRITERAM" uses code string "00011000000"
Warning (14130): Reduced register "serial_test:inst4|txd_buf[7]" with stuck data_in port to stuck value GND
Info: Inferred 4 megafunctions from design logic
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Div0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Mod1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Mod0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "counter:inst2|Div1"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "counter:inst2|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf
    Info: Found entity 1: lpm_divide_vcm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf
    Info: Found entity 1: sign_div_unsign_9kh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf
    Info: Found entity 1: alt_u_div_kve
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "counter:inst2|lpm_divide:Mod1"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf
    Info: Found entity 1: lpm_divide_25m
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "seg_data[7]" stuck at VCC
Info: 29 registers lost all their fanouts during netlist optimizations. The first 29 are displayed below.
    Info: Register "lcd:inst3|state.RETURNCURSOR" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state.SETCGRAM" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state.SETDDRAM2" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state~61" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state~62" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state~63" lost all its fanouts during netlist optimizations.
    Info: Register "lcd:inst3|state~65" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[15]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[16]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[17]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[18]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[19]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[20]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[21]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[22]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[23]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[24]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[25]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[26]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[27]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[28]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[29]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[30]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[31]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[32]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[33]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[34]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[35]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[36]" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file F:/FPGA/ep2c5_project/dl2c58_c5/sclock.map.smsg
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "rxd"
Info: Implemented 458 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 29 output pins
    Info: Implemented 426 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
    Info: Allocated 167 megabytes of memory during processing
    Info: Processing ended: Wed Dec 03 23:20:16 2008
    Info: Elapsed time: 00:00:16


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; Analysis & Synthesis Suppressed Messages ;
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The suppressed messages can be found in F:/FPGA/ep2c5_project/dl2c58_c5/sclock.map.smsg.