clock.v

来自「FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.」· Verilog 代码 · 共 71 行

module Clock(clk, reset, secmin);
	input clk, reset;
	output [15:0] secmin;
	reg [15:0] secmin;
	
	reg [3:0] HourLow ;
	reg [3:0] HourHigh;
	reg [3:0] MinLow  ;
	reg [3:0] MinHigh ;
	reg [3:0] SecLow  ;
	reg [3:0] SecHigh ;
	
	always @(posedge clk or negedge reset) begin
		if (!reset) begin
				HourLow   <= 4'h0;
	            HourHigh  <= 4'h0;
	            MinLow    <= 4'h0;
	            MinHigh   <= 4'h0;
	            SecLow    <= 4'h0;
	            SecHigh   <= 4'h0;
		end
		else begin
			if (SecLow == 4'h9) begin
				SecLow <= 4'h0;
				if (SecHigh == 4'h5) begin
					SecHigh <= 4'h0;
					if (MinLow == 4'h9) begin
						MinLow <= 4'h0;
						if (MinHigh == 4'h5) begin
							MinHigh <= 4'h0;
							if (HourLow == 4'h9) begin
								HourLow <= 4'h0;
								if (HourHigh == 4'h2) begin
									HourHigh <= 4'h0;
								end
								else begin
								   HourHigh <= HourHigh + 1'b1;
								end
							end
							else begin
								HourLow <= HourLow + 1'b1;
							end
						end
						else begin
							MinHigh <= MinHigh + 1'b1;
						end
					end
					else begin 
						MinLow <= MinLow + 1'b1;
					end
				end
				else begin 
					SecHigh <= SecHigh + 1'b1;
				end
			end
			else begin
				SecLow <= SecLow + 1'b1;
			end
		end

	end
	always @(*) begin 
        if (!reset) begin
            secmin <= 16'h0;
        end
        else begin
			secmin <= {MinHigh, MinLow, SecHigh, SecLow};
        end
    end	
endmodule